Wafer Scale Integration Iii
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| Author | : Mariagiovanna Sami |
| Publisher | : North Holland |
| Total Pages | : 518 |
| Release | : 1990 |
| Genre | : Technology & Engineering |
| ISBN | : |
The purpose of this book is to give an up-to-date presentation of architectures and technologies for wafer-scale integration. As such, it is an overview of the work of the leading research centers active in this area, and an outline of expected evolution and progress in the subject. New technological solutions are envisioned; while the use of optical technologies for interconnections promises to overcome one of the main restrictions to architectures on a wafer, the extension of quick-prototyping solutions to the wafer dimension allows the introduction of wafer-scale systems in educational environments as well as in applications where a quick result and limited production would make traditional silicon solutions unacceptable. Regarding architectures and their applications, three different lines of approach can be identified. Evolutive solutions are proposed, mainly concerning array architectures and restructuring techniques. Innovative architectures are presented, several papers dealing with neural nets. There are also architectures designed not just for experimental reasons but for industrial production. Overall, non-numerical applications predominate.
| Author | : Earl E. Swartzlander Jr. |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 515 |
| Release | : 2012-12-06 |
| Genre | : Technology & Engineering |
| ISBN | : 1461316219 |
Wafer Scale Integration (WSI) is the culmination of the quest for larger integrated circuits. In VLSI chips are developed by fabricating a wafer with hundreds of identical circuits, testing the circuits, dicing the wafer, and packaging the good dice. In contrast in WSI, a wafer is fabricated with several types of circuits (generally referred to as cells), with multiple instances of each cell type, the cells are tested, and good cells are interconnected to realize a system on the wafer. Since most signal lines stay on the wafer, stray capacitance is low, so that high speeds are achieved with low power consumption. For the same technology a WSI implementation may be a factor of five faster, dissipate a factor of ten less power, and require one hundredth to one thousandth the volume. Successful development of WSI involves many overlapping disciplines, ranging from architecture to test design to fabrication (including laser linking and cutting, multiple levels of interconnection, and packaging). This book concentrates on the areas that are unique to WSI and that are as a result not well covered by any of the many books on VLSI design. A unique aspect of WSI is that the finished circuits are so large that there will be defects in some portions of the circuit. Accordingly much attention must be devoted to designing architectures that facilitate fault detection and reconfiguration to of WSI include fabrication circumvent the faults. Other unique aspects technology and packaging.
| Author | : Chuan Seng Tan |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 365 |
| Release | : 2009-06-29 |
| Genre | : Technology & Engineering |
| ISBN | : 0387765344 |
This book focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses the technology platform for pre-packaging wafer lever 3-D ICs. However, this book does not include a detailed discussion of 3-D ICs design and 3-D packaging. This is an edited book based on chapters contributed by various experts in the field of wafer-level 3-D ICs process technology. They are from academia, research labs and industry.
| Author | : Electrochemical Society. Meeting |
| Publisher | : The Electrochemical Society |
| Total Pages | : 620 |
| Release | : 2003 |
| Genre | : Technology & Engineering |
| ISBN | : 9781566773768 |
| Author | : Masayoshi Esashi |
| Publisher | : John Wiley & Sons |
| Total Pages | : 528 |
| Release | : 2021-03-16 |
| Genre | : Technology & Engineering |
| ISBN | : 3527823255 |
Explore heterogeneous circuit integration and the packaging needed for practical applications of microsystems MEMS and system integration are important building blocks for the “More-Than-Moore” paradigm described in the International Technology Roadmap for Semiconductors. And, in 3D and Circuit Integration of MEMS, distinguished editor Dr. Masayoshi Esashi delivers a comprehensive and systematic exploration of the technologies for microsystem packaging and heterogeneous integration. The book focuses on the silicon MEMS that have been used extensively and the technologies surrounding system integration. You’ll learn about topics as varied as bulk micromachining, surface micromachining, CMOS-MEMS, wafer interconnection, wafer bonding, and sealing. Highly relevant for researchers involved in microsystem technologies, the book is also ideal for anyone working in the microsystems industry. It demonstrates the key technologies that will assist researchers and professionals deal with current and future application bottlenecks. Readers will also benefit from the inclusion of: A thorough introduction to enhanced bulk micromachining on MIS process, including pressure sensor fabrication and the extension of MIS process for various advanced MEMS devices An exploration of epitaxial poly Si surface micromachining, including process condition of epi-poly Si, and MEMS devices using epi-poly Si Practical discussions of Poly SiGe surface micromachining, including SiGe deposition and LP CVD polycrystalline SiGe A concise treatment of heterogeneously integrated aluminum nitride MEMS resonators and filters Perfect for materials scientists, electronics engineers, and electrical and mechanical engineers, 3D and Circuit Integration of MEMS will also earn a place in the libraries of semiconductor physicists seeking a one-stop reference for circuit integration and the practical application of microsystems.
| Author | : R. M. Lea |
| Publisher | : North Holland |
| Total Pages | : 268 |
| Release | : 1988 |
| Genre | : Computers |
| ISBN | : |
| Author | : Stuart K. Tewksbury |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 456 |
| Release | : 2012-12-06 |
| Genre | : Technology & Engineering |
| ISBN | : 1461316251 |
From the perspective of complex systems, conventional Ie's can be regarded as "discrete" devices interconnected according to system design objectives imposed at the circuit board level and higher levels in the system implementation hierarchy. However, silicon monolithic circuits have progressed to such complex functions that a transition from a philosophy of integrated circuits (Ie's) to one of integrated sys tems is necessary. Wafer-scale integration has played an important role over the past few years in highlighting the system level issues which will most significantly impact the implementation of complex monolithic systems and system components. Rather than being a revolutionary approach, wafer-scale integration will evolve naturally from VLSI as defect avoidance, fault tolerance and testing are introduced into VLSI circuits. Successful introduction of defect avoidance, for example, relaxes limits imposed by yield and cost on Ie dimensions, allowing the monolithic circuit's area to be chosen according to the natural partitioning of a system into individual functions rather than imposing area limits due to defect densities. The term "wafer level" is perhaps more appropriate than "wafer-scale". A "wafer-level" monolithic system component may have dimensions ranging from conventional yield-limited Ie dimensions to full wafer dimensions. In this sense, "wafer-scale" merely represents the obvious upper practical limit imposed by wafer sizes on the area of monolithic circuits. The transition to monolithic, wafer-level integrated systems will require a mapping of the full range of system design issues onto the design of monolithic circuit.
| Author | : Israel Koren |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 362 |
| Release | : 2012-12-06 |
| Genre | : Computers |
| ISBN | : 1461567998 |
This book contains an edited selection of papers presented at the International Workshop on Defect and Fault Tolerance in VLSI Systems held October 6-7, 1988 in Springfield, Massachusetts. Our thanks go to all the contributors and especially the members of the program committee for the difficult and time-consuming work involved in selecting the papers that were presented in the workshop and reviewing the papers included in this book. Thanks are also due to the IEEE Computer Society (in particular, the Technical Committee on Fault-Tolerant Computing and the Technical Committee on VLSI) and the University of Massachusetts at Amherst for sponsoring the workshop, and to the National Science Foundation for supporting (under grant number MIP-8803418) the keynote address and the distribution of this book to all workshop attendees. The objective of the workshop was to bring t. ogether researchers and practition ers from both industry and academia in the field of defect tolerance and yield en ha. ncement in VLSI to discuss their mutual interests in defect-tolerant architectures and models for integrated circuit defects, faults, and yield. Progress in this area was slowed down by the proprietary nature of yield-related data, and by the lack of appropriate forums for disseminating such information. The goal of this workshop was therefore to provide a forum for a dialogue and exchange of views. A follow-up workshop in October 1989, with C. H. Stapper from IBM and V. K. Jain from the University of South Florida as general co-chairmen, is being organized.
| Author | : C.H. Stapper |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 313 |
| Release | : 2013-06-29 |
| Genre | : Technology & Engineering |
| ISBN | : 1475799578 |
Higher circuit densities, increasingly more complex application ohjectives, and advanced packaging technologies have suhstantially increased the need to incorporate defect-tolerance and fault-tolerance in the design of VLSI and WSI systems. The goals of defect-tolerance and fault-tolerance are yield enhancement and improved reliahility. The emphasis on this area has resulted in a new field of interdisciplinary scientific research. I n fact, advanced methods of defect/fault control and tolerance are resulting in enhanced manufacturahility and productivity of integrated circuit chips, VI.SI systems, and wafer scale integrated circuits. In 1987, Dr. W. Moore organized an "International Workshop on Designing for Yield" at Oxford University. Edited papers of that workshop were published in reference [II. The participants in that workshop agreed that meetings of this type should he con tinued. preferahly on a yearly hasis. It was Dr. I. Koren who organized the "IEEE Inter national Workshop on Defect and Fault Tolerance in VLSI Systems" in Springfield Massachusetts the next year. Selected papers from that workshop were puhlished as the first volume of this series [21.
| Author | : Zhensheng Jia |
| Publisher | : CRC Press |
| Total Pages | : 136 |
| Release | : 2019-10-28 |
| Genre | : Technology & Engineering |
| ISBN | : 1000736962 |
This book will highlight the motivation for coherent optics in access and introduce digital coherent optical system in detail, including advanced modulation formats, architecture of modulation and detection, and DSP flow for both transmitter and receiver. This book will also demonstrate potential approaches to re-design and re-engineer the digital coherent concept from long-haul and metro solutions to the access network, leveraging reduction in complexity and cost as well as the benefits of capacity increases and operational improvements. This book will illustrate the details on optimization of the digital, optical, and electrical complexity and standardization and interoperability.
