Timing Verification And Synthesis Of Circuits For Delay Fault Testability
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| Author | : Luciano Lavagno |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 353 |
| Release | : 2012-12-06 |
| Genre | : Technology & Engineering |
| ISBN | : 1461532124 |
Since the second half of the 1980s asynchronous circuits have been the subject of a great deal of research following a period of relative oblivion. The lack of interest in asynchronous techniques was motivated by the progressive shift towards synchronous design techniques that had much more structure and were much easier to verify and synthesize. System design requirements made it impossible to eliminate totally the use of asynchronous circuits. Given the objective difficulty encountered by designers, the asynchronous components of electronic systems such as interfaces became a serious bottleneck in the design process. The use of new models and some theoretical breakthroughs made it possible to develop asynchronous design techniques that were reliable and effective. This book describes a variety of mathematical models and of algorithms that form the backbone and the body of a new design methodology for asyn chronous design. The book is intended for asynchronous hardware designers, for computer-aided tool experts, and for digital designers interested in ex ploring the possibility of designing asynchronous circuits. It requires a solid mathematical background in discrete event systems and algorithms. While the book has not been written as a textbook, nevertheless it could be used as a reference book in an advanced course in logic synthesis or asynchronous design.
| Author | : William K.C. Lam |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 290 |
| Release | : 2012-12-06 |
| Genre | : Technology & Engineering |
| ISBN | : 1461526884 |
Timing research in high performance VLSI systems has advanced at a steady pace over the last few years, while tools, especially theoretical mechanisms, lag behind. Much present timing research relies heavily on timing diagrams, which, although intuitive, are inadequate for analysis of large designs with many parameters. Further, timing diagrams offer only approximations, not exact solutions, to many timing problems and provide little insight in the cases where temporal properties of a design interact intricately with the design's logical functionalities. This book presents a methodology for timing research which facilitates analy sis and design of circuits and systems in a unified temporal and logical domain. In the first part, we introduce an algebraic representation formalism, Timed Boolean Functions (TBF's), which integrates both logical and timing informa tion of digital circuits and systems into a single formalism. We also give a canonical form, TBF BDD's, for them, which can be used for efficient ma nipulation. In the second part, we apply Timed Boolean Functions to three problems in timing research, for which exact solutions are obtained for the first time: 1. computing the exact delays of combinational circuits and the minimum cycle times of finite state machines, 2. analysis and synthesis of wavepipelining circuits, a high speed architecture for which precise timing relations between signals are essential for correct operations, 3. verification of circuit and system performance and coverage of delay faults by testing.
| Author | : Klaus Echtle |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 642 |
| Release | : 1994-09-21 |
| Genre | : Computers |
| ISBN | : 9783540584261 |
This book presents the proceedings of the First European Dependable Computing Conference (EDCC-1), held in Berlin, Germany, in October 1994. EDCC is the merger of two former European events on dependable computing. The volume comprises 34 refereed full papers selected from 106 submissions. The contributions address all current aspects of dependable computing and reflect the state of the art in dependable systems research and advanced applications; among the topics covered are hardware and software reliability, safety-critical and secure systems, fault-tolerance and detection, verification and validation, formal methods, hardware and software testing, and parallel and distributed systems.
| Author | : Andreas Kuehlmann |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 699 |
| Release | : 2012-12-06 |
| Genre | : Computers |
| ISBN | : 1461502926 |
In 2002, the International Conference on Computer Aided Design (ICCAD) celebrates its 20th anniversary. This book commemorates contributions made by ICCAD to the broad field of design automation during that time. The foundation of ICCAD in 1982 coincided with the growth of Large Scale Integration. The sharply increased functionality of board-level circuits led to a major demand for more powerful Electronic Design Automation (EDA) tools. At the same time, LSI grew quickly and advanced circuit integration became widely avail able. This, in turn, required new tools, using sophisticated modeling, analysis and optimization algorithms in order to manage the evermore complex design processes. Not surprisingly, during the same period, a number of start-up com panies began to commercialize EDA solutions, complementing various existing in-house efforts. The overall increased interest in Design Automation (DA) re quired a new forum for the emerging community of EDA professionals; one which would be focused on the publication of high-quality research results and provide a structure for the exchange of ideas on a broad scale. Many of the original ICCAD volunteers were also members of CANDE (Computer-Aided Network Design), a workshop of the IEEE Circuits and Sys tem Society. In fact, it was at a CANDE workshop that Bill McCalla suggested the creation of a conference for the EDA professional. (Bill later developed the name).
| Author | : Alain Finkel |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 644 |
| Release | : 1992-02-04 |
| Genre | : Computers |
| ISBN | : 9783540552109 |
This volume gives the proceedings of the ninth Symposium on Theoretical Aspects of Computer Science (STACS). This annual symposium is held alternately in France and Germany and is organized jointly by the Special Interest Group for Fundamental Computer Science of the Association Francaise des Sciences et Technologies de l'Information et des Syst mes (AFCET) and the Special Interest Group for Theoretical Computer Science of the Gesellschaft f}r Informatik (GI). The volume includes three invited lectures and sections on parallel algorithms, logic and semantics, computational geometry, automata and languages, structural complexity, computational geometry and learning theory, complexity and communication, distributed systems, complexity, algorithms, cryptography, VLSI, words and rewriting, and systems.
| Author | : Rolf Drechsler |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 182 |
| Release | : 2013-03-14 |
| Genre | : Computers |
| ISBN | : 1475735960 |
The design process of digital circuits is often carried out in individual steps, like logic synthesis, mapping, and routing. Since originally the complete process was too complex, it has been split up in several - more or less independen- phases. In the last 40 years powerful algorithms have been developed to find optimal solutions for each of these steps. However, the interaction of these different algorithms has not been considered for a long time. This leads to quality loss e. g. in cases where highly optimized netlists fit badly onto the target architecture. Since the resulting circuits are often far from being optimal and insufficient regarding the optimization criteria, like area and delay, several iterations of the complete design process have to be carried out to get high quality results. This is a very time consuming and costly process. For this reason, some years ago the idea of one-pass synthesis came up. There were two main approaches how to guarantee that a design got "first time right" : 1. Combining levels that were split before, e. g. to use layout information already during the logic synthesis phase. 2. Restricting the optimization in one level such that it better fits to the next one. So far, several approaches in these two directions have been presented and new techniques are under development. In this book we describe the new paradigm that is used in one-pass synthesis and present examples for the two techniques above.
| Author | : |
| Publisher | : |
| Total Pages | : 542 |
| Release | : 1999 |
| Genre | : Application-specific integrated circuits |
| ISBN | : |
| Author | : Rolf Drechsler |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 185 |
| Release | : 2013-03-09 |
| Genre | : Computers |
| ISBN | : 1475731841 |
Formal verification has become one of the most important steps in circuit design. Since circuits can contain several million transistors, verification of such large designs becomes more and more difficult. Pure simulation cannot guarantee the correct behavior and exhaustive simulation is often impossible. However, many designs, like ALUs, have very regular structures that can be easily described at a higher level of abstraction. For example, describing (and verifying) an integer multiplier at the bit-level is very difficult, while the verification becomes easy when the outputs are grouped to build a bit-string. Recently, several approaches for formal circuit verification have been proposed that make use of these regularities. These approaches are based on Word-Level Decision Diagrams (WLDDs) which are graph-based representations of functions (similar to BDDs) that allow for the representation of functions with a Boolean range and an integer domain. Formal Verification of Circuits is devoted to the discussion of recent developments in the field of decision diagram-based formal verification. Firstly, different types of decision diagrams (including WLDDs) are introduced and theoretical properties are discussed that give further insight into the data structure. Secondly, implementation and minimization concepts are presented. Applications to arithmetic circuit verification and verification of designs specified by hardware description languages are described to show how WLDDs work in practice. Formal Verification of Circuits is intended for CAD developers and researchers as well as designers using modern verification tools. It will help people working with formal verification (in industry or academia) to keep informed about recent developments in this area.
| Author | : |
| Publisher | : |
| Total Pages | : 720 |
| Release | : 1994 |
| Genre | : Application-specific integrated circuits |
| ISBN | : |
| Author | : Angela Krstic |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 201 |
| Release | : 2012-12-06 |
| Genre | : Technology & Engineering |
| ISBN | : 1461555973 |
In the early days of digital design, we were concerned with the logical correctness of circuits. We knew that if we slowed down the clock signal sufficiently, the circuit would function correctly. With improvements in the semiconductor process technology, our expectations on speed have soared. A frequently asked question in the last decade has been how fast can the clock run. This puts significant demands on timing analysis and delay testing. Fueled by the above events, a tremendous growth has occurred in the research on delay testing. Recent work includes fault models, algorithms for test generation and fault simulation, and methods for design and synthesis for testability. The authors of this book, Angela Krstic and Tim Cheng, have personally contributed to this research. Now they do an even greater service to the profession by collecting the work of a large number of researchers. In addition to expounding such a great deal of information, they have delivered it with utmost clarity. To further the reader's understanding many key concepts are illustrated by simple examples. The basic ideas of delay testing have reached a level of maturity that makes them suitable for practice. In that sense, this book is the best x DELAY FAULT TESTING FOR VLSI CIRCUITS available guide for an engineer designing or testing VLSI systems. Tech niques for path delay testing and for use of slower test equipment to test high-speed circuits are of particular interest.
