Reliability-performance Trade-offs in Photonic NoC Architectures

Reliability-performance Trade-offs in Photonic NoC Architectures
Author: Pradheep Khanna Kaliraj
Publisher:
Total Pages: 128
Release: 2013
Genre: Networks on a chip
ISBN:

"Advancements in the field of chip fabrication has facilitated in integrating more number of transistors in a given area which lead to the era of multi-core processors. Interconnect became the bottleneck for the multi-core processors as the number of cores in a chip increased. The traditional bus based architectures, which are currently used in the processors, cannot scale up to support the increasing number of cores in a multi-core chip. Hence, Network-on-Chip (NoC) is the preferred communication backbone for modern multicore chips. However, the multi-hop data transmission using wireline interconnects result in high energy dissipation and latency. Hence, many alternative interconnect technologies have been proposed such as 3D, wireless, and photonic interconnects. These interconnect technologies have their own advantages and disadvantages. Photonic interconnects have emerged as a promising alternative to the conventional metal/dielectric based on-chip wireline interconnects. Several novel architectures have been proposed using photonic waveguides as interconnects, which are capable of reducing the energy dissipation in data transfer significantly. However, the issues of reliability arising due to waveguide losses and adjacent channel crosstalk in photonic waveguides have not received much attention till date. In this paper we propose and evaluate the performance of a photonic NoC architecture designed by segmenting the waveguides into smaller parts to limit the waveguide losses and signal degradation from electro-optic devices. Through detailed system level simulations in this work we compare the performance of the MSB-PNoC with other PNoC architectures proposed in the recent literature and establish its gains over completely electronic mesh based counterparts."--Abstract.

Photonic Interconnects for Computing Systems

Photonic Interconnects for Computing Systems
Author: Gabriela Nicolescu
Publisher: CRC Press
Total Pages: 453
Release: 2022-09-01
Genre: Technology & Engineering
ISBN: 1000793370

In recent years, there has been a considerable amount of effort, both in industry and academia, focusing on the design, implementation, performance analysis, evaluation and prediction of silicon photonic interconnects for inter- and intra-chip communication, paving the way for the design and dimensioning of the next and future generation of high-performance computing systems. Photonic Interconnects for Computing Systems provides a comprehensive overview of the current state-of-the-art technology and research achievements in employing silicon photonics for interconnection networks and high-performance computing, summarizing main opportunities and some challenges. The majority of the chapters were collected from presentations made at the International Workshop on Optical/Photonic Interconnects for Computing Systems (OPTICS) held over the past two years. The workshop invites internationally recognized speakers on the range of topics relevant to silicon photonics and computing systems. Technical topics discussed in the book include:Design and Implementation of Chip-Scale Photonic Interconnects;Developing Design Automation Solutions for Chip-Scale Photonic Interconnects;Design Space Exploration in Chip-Scale Photonic Interconnects;Thermal Analysis and Modeling in Photonic Interconnects;Design for Reliability;Fabrication Non-Uniformity in Photonic Interconnects;Photonic Interconnects for Computing Systems presents a compilation of outstanding contributions from leading research groups in the field. It presents a comprehensive overview of the design, advantages, challenges, and requirements of photonic interconnects for computing systems. The selected contributions present important discussions and approaches related to the design and development of novel photonic interconnect architectures, as well as various design solutions to improve the performance of such systems while considering different challenges. The book is ideal for personnel in computer/photonic industries as well as academic staff and master/graduate students in computer science and engineering, electronic engineering, electrical engineering and photonics.

Advanced Multicore Systems-On-Chip

Advanced Multicore Systems-On-Chip
Author: Abderazek Ben Abdallah
Publisher: Springer
Total Pages: 292
Release: 2017-09-10
Genre: Computers
ISBN: 9811060924

From basic architecture, interconnection, and parallelization to power optimization, this book provides a comprehensive description of emerging multicore systems-on-chip (MCSoCs) hardware and software design. Highlighting both fundamentals and advanced software and hardware design, it can serve as a primary textbook for advanced courses in MCSoCs design and embedded systems. The first three chapters introduce MCSoCs architectures, present design challenges and conventional design methods, and describe in detail the main building blocks of MCSoCs. Chapters 4, 5, and 6 discuss fundamental and advanced on-chip interconnection network technologies for multi and many core SoCs, enabling readers to understand the microarchitectures for on-chip routers and network interfaces that are essential in the context of latency, area, and power constraints. With the rise of multicore and many-core systems, concurrency is becoming a major issue in the daily life of a programmer. Thus, compiler and software development tools are critical in helping programmers create high-performance software. Programmers should make sure that their parallelized program codes will not cause race condition, memory-access deadlocks, or other faults that may crash their entire systems. As such, Chapter 7 describes a novel parallelizing compiler design for high-performance computing. Chapter 8 provides a detailed investigation of power reduction techniques for MCSoCs at component and network levels. It discusses energy conservation in general hardware design, and also in embedded multicore system components, such as CPUs, disks, displays and memories. Lastly, Chapter 9 presents a real embedded MCSoCs system design targeted for health monitoring in the elderly.

Design Trade-offs for Reliable On-chip Wireless Interconnects in NoC Platforms

Design Trade-offs for Reliable On-chip Wireless Interconnects in NoC Platforms
Author: Manoj Prashanth Yuvaraj
Publisher:
Total Pages: 146
Release: 2014
Genre: Code division multiple access
ISBN:

"The massive levels of integration following Moore's Law making modern multi-core chips prevail in various domains ranging from scientific applications to bioinformatics applications for consumer electronics. With higher and higher number of cores on the same die traditional bus based interconnections are no longer a scalable communication infrastructure. On-chip networks were proposed enabled a scalable plug-and-play mechanism for interconnecting hundreds of cores on the same chip. Wired interconnects between the cores in a traditional Network-on-Chip (NoC) system, becomes a bottleneck with increase in the number of cores thereby increasing the latency and energy to transmit signals over them. Hence, there has been many alternative emerging interconnect technologies proposed, namely, 3D, photonic and multi-band RF interconnects. Although they provide better connectivity, higher speed and higher bandwidth compared to wired interconnects; they also face challenges with heat dissipation and manufacturing difficulties. On-chip wireless interconnects is one other alternative proposed which doesn't need physical interconnection layout as data travels over the wireless medium. They are integrated into a hybrid NOC architecture consisting of both wired and wireless links, which provides higher bandwidth, lower latency, lesser area overhead and reduced energy dissipation in communication. An efficient media access control (MAC) scheme is required to enhance the utilization of the available bandwidth. A token-passing protocol proposed to grant access of the wireless channel to competing transmitters. This limits the number of simultaneous users of the communication channel to one although multiple wireless hubs are deployed over the chip. In principle, a Frequency Division Multiple Access (FDMA) based medium access scheme would improve the utilization of the wireless resources. However, this requires design of multiple very precise, high frequency transceivers in non-overlapping frequency channels. Therefore, the scalability of this approach is limited by the state-of-the-art in transceiver design. The Code Division Multiple Access (CDMA) enables multiple transmitter-receiver pairs to send data over the wireless channel simultaneously. The CDMA protocol can significantly increase the performance of the system while lowering the energy dissipation in data transfer. The CDMA based MAC protocol outperforms the wired counterparts and several other wireless architectures proposed in literature in terms of bandwidth and packet energy dissipation. However, the reliability of CDMA based wireless NoC's is limited, as the probability of error is eminent due to synchronization delays at the receiver. The thesis proposes the use of an advanced filter which improves the performance and also reduces the error due to synchronization delays. This thesis also proposes investigation of various channel modulation schemes on token passing wireless NoC's to examine the performance and reliability of the system. The trade-off between performance and energy are established for the various conditions. The results are obtained using a modified cycle accurate simulator."--Abstract.

Silicon Photonics for High-Performance Computing and Beyond

Silicon Photonics for High-Performance Computing and Beyond
Author: Mahdi Nikdast
Publisher: CRC Press
Total Pages: 391
Release: 2021-11-16
Genre: Technology & Engineering
ISBN: 1000480143

Silicon photonics is beginning to play an important role in driving innovations in communication and computation for an increasing number of applications, from health care and biomedical sensors to autonomous driving, datacenter networking, and security. In recent years, there has been a significant amount of effort in industry and academia to innovate, design, develop, analyze, optimize, and fabricate systems employing silicon photonics, shaping the future of not only Datacom and telecom technology but also high-performance computing and emerging computing paradigms, such as optical computing and artificial intelligence. Different from existing books in this area, Silicon Photonics for High-Performance Computing and Beyond presents a comprehensive overview of the current state-of-the-art technology and research achievements in applying silicon photonics for communication and computation. It focuses on various design, development, and integration challenges, reviews the latest advances spanning materials, devices, circuits, systems, and applications. Technical topics discussed in the book include: • Requirements and the latest advances in high-performance computing systems • Device- and system-level challenges and latest improvements to deploy silicon photonics in computing systems • Novel design solutions and design automation techniques for silicon photonic integrated circuits • Novel materials, devices, and photonic integrated circuits on silicon • Emerging computing technologies and applications based on silicon photonics Silicon Photonics for High-Performance Computing and Beyond presents a compilation of 19 outstanding contributions from academic and industry pioneers in the field. The selected contributions present insightful discussions and innovative approaches to understand current and future bottlenecks in high-performance computing systems and traditional computing platforms, and the promise of silicon photonics to address those challenges. It is ideal for researchers and engineers working in the photonics, electrical, and computer engineering industries as well as academic researchers and graduate students (M.S. and Ph.D.) in computer science and engineering, electronic and electrical engineering, applied physics, photonics, and optics.

Bio-Inspired Fault-Tolerant Algorithms for Network-on-Chip

Bio-Inspired Fault-Tolerant Algorithms for Network-on-Chip
Author: Muhammad Athar Javed Sethi
Publisher: CRC Press
Total Pages: 212
Release: 2020-03-17
Genre: Computers
ISBN: 1000048055

Network on Chip (NoC) addresses the communication requirement of different nodes on System on Chip. The bio-inspired algorithms improve the bandwidth utilization, maximize the throughput and reduce the end-to-end latency and inter-flit arrival time. This book exclusively presents in-depth information regarding bio-inspired algorithms solving real world problems focussing on fault-tolerant algorithms inspired by the biological brain and implemented on NoC. It further documents the bio-inspired algorithms in general and more specifically, in the design of NoC. It gives an exhaustive review and analysis of the NoC architectures developed during the last decade according to various parameters. Key Features: Covers bio-inspired solutions pertaining to Network-on-Chip (NoC) design solving real world examples Includes bio-inspired NoC fault-tolerant algorithms with detail coding examples Lists fault-tolerant algorithms with detailed examples Reviews basic concepts of NoC Discusses NoC architectures developed-to-date

Handbook of Energy-Aware and Green Computing - Two Volume Set

Handbook of Energy-Aware and Green Computing - Two Volume Set
Author: Ishfaq Ahmad
Publisher: CRC Press
Total Pages: 1284
Release: 2016-02-03
Genre: Computers
ISBN: 1482254441

Implementing energy-efficient CPUs and peripherals as well as reducing resource consumption have become emerging trends in computing. As computers increase in speed and power, their energy issues become more and more prevalent. The need to develop and promote environmentally friendly computer technologies and systems has also come to the forefront

Temperature Evaluation of NoC Architectures and Dynamically Reconfigurable NoC

Temperature Evaluation of NoC Architectures and Dynamically Reconfigurable NoC
Author: Aniket Dilip Mhatre
Publisher:
Total Pages: 124
Release: 2014
Genre: Interconnects (Integrated circuit technology)
ISBN:

"Advancements in the field of chip fabrication led to the integration of a large number of transistors in a small area, giving rise to the multi-core processor era. Massive multi-core processors facilitate innovation and research in the field of healthcare, defense, entertainment, meteorology and many others. Reduction in chip area and increase in the number of on-chip cores is accompanied by power and temperature issues. In high performance multi-core chips, power and heat are predominant constraints. High performance massive multicore systems suffer from thermal hotspots, exacerbating the problem of reliability in deep submicron technologies. High power consumption not only increases the chip temperature but also jeopardizes the integrity of the system. Hence, there is a need to explore holistic power and thermal optimization and management strategies for massive on-chip multi-core environments. In multi-core environments, the communication fabric plays a major role in deciding the efficiency of the system. In multi-core processor chips this communication infrastructure is predominantly a Network-on-Chip (NoC). Tradition NoC designs incorporate planar interconnects as a result these NoCs have long, multi-hop wireline links for data exchange. Due to the presence of multi-hop planar links such NoC architectures fall prey to high latency, significant power dissipation and temperature hotspots. Networks inspired from nature are envisioned as an enabling technology to achieve highly efficient and low power NoC designs. Adopting wireless technology in such architectures enhance their performance. Placement of wireless interconnects (WIs) alters the behavior of the network and hence a random deployment of WIs may not result in a thermally optimal solution. In such scenarios, the WIs being highly efficient would attract high traffic densities resulting in thermal hotspots. Hence, the location and utilization of the wireless links is a key factor in obtaining a thermal optimal highly efficient Network-on-chip. Optimization of the NoC framework alone is incapable of addressing the effects due to the runtime dynamics of the system. Minimal paths solely optimized for performance in the network may lead to excessive utilization of certain NoC components leading to thermal hotspots. Hence, architectural innovation in conjunction with suitable power and thermal management strategies is the key for designing high performance and energy-efficient multicore systems. This work contributes at exploring various wired and wireless NoC architectures that achieve best trade-offs between temperature, performance and energy-efficiency. It further proposes an adaptive routing scheme which factors in the thermal profile of the chip. The proposed routing mechanism dynamically reacts to the thermal profile of the chip and takes measures to avoid thermal hotspots, achieving a thermally efficient dynamically reconfigurable network on chip architecture."--Abstract.

Evolutionary Based Solutions for Green Computing

Evolutionary Based Solutions for Green Computing
Author: Samee Ullah Khan
Publisher: Springer
Total Pages: 268
Release: 2012-08-14
Genre: Technology & Engineering
ISBN: 3642306594

Today’s highly parameterized large-scale distributed computing systems may be composed of a large number of various components (computers, databases, etc) and must provide a wide range of services. The users of such systems, located at different (geographical or managerial) network cluster may have a limited access to the system’s services and resources, and different, often conflicting, expectations and requirements. Moreover, the information and data processed in such dynamic environments may be incomplete, imprecise, fragmentary, and overloading. All of the above mentioned issues require some intelligent scalable methodologies for the management of the whole complex structure, which unfortunately may increase the energy consumption of such systems. An optimal energy utilization has reached to a point that many information technology (IT) managers and corporate executives are all up in arms to identify scalable solution that can reduce electricity consumption (so that the total cost of operation is minimized) of their respective large-scale computing systems and simultaneously improve upon or maintain the current throughput of the system. This book in its eight chapters, addresses the fundamental issues related to the energy usage and the optimal low-cost system design in high performance ``green computing’’ systems. The recent evolutionary and general metaheuristic-based solutions for energy optimization in data processing, scheduling, resource allocation, and communication in modern computational grids, could and network computing are presented along with several important conventional technologies to cover the hot topics from the fundamental theory of the ‘’green computing’’ concept and to describe the basic architectures of systems. This book points out the potential application areas and provides detailed examples of application case studies in low-energy computational systems. The development trends and open research issues are also outlined. All of those technologies have formed the foundation for the green computing that we know of today.

Networks on Chips

Networks on Chips
Author: Giovanni De Micheli
Publisher: Elsevier
Total Pages: 408
Release: 2006-08-30
Genre: Technology & Engineering
ISBN: 0080473563

The design of today's semiconductor chips for various applications, such as telecommunications, poses various challenges due to the complexity of these systems. These highly complex systems-on-chips demand new approaches to connect and manage the communication between on-chip processing and storage components and networks on chips (NoCs) provide a powerful solution. This book is the first to provide a unified overview of NoC technology. It includes in-depth analysis of all the on-chip communication challenges, from physical wiring implementation up to software architecture, and a complete classification of their various Network-on-Chip approaches and solutions. * Leading-edge research from world-renowned experts in academia and industry with state-of-the-art technology implementations/trends * An integrated presentation not currently available in any other book * A thorough introduction to current design methodologies and chips designed with NoCs