VLSI Placement and Global Routing Using Simulated Annealing

VLSI Placement and Global Routing Using Simulated Annealing
Author: Carl Sechen
Publisher: Springer Science & Business Media
Total Pages: 298
Release: 2012-12-06
Genre: Technology & Engineering
ISBN: 1461316979

From my B.E.E degree at the University of Minnesota and right through my S.M. degree at M.I.T., I had specialized in solid state devices and microelectronics. I made the decision to switch to computer-aided design (CAD) in 1981, only a year or so prior to the introduction of the simulated annealing algorithm by Scott Kirkpatrick, Dan Gelatt, and Mario Vecchi of the IBM Thomas 1. Watson Research Center. Because Prof. Alberto Sangiovanni-Vincentelli, my UC Berkeley advisor, had been a consultant at IBM, I re ceived a copy of the original IBM internal report on simulated annealing approximately the day of its release. Given my background in statistical mechanics and solid state physics, I was immediately impressed by this new combinatorial optimization technique. As Prof. Sangiovanni-Vincentelli had suggested I work in the areas of placement and routing, it was in these realms that I sought to explore this new algorithm. My flJ'St implementation of simulated annealing was for an island-style gate array placement problem. This work is presented in the Appendix of this book. I was quite struck by the effect of a nonzero temperature on what otherwise appears to be a random in terchange algorithm.

VLSI Physical Design: From Graph Partitioning to Timing Closure

VLSI Physical Design: From Graph Partitioning to Timing Closure
Author: Andrew B. Kahng
Publisher: Springer Science & Business Media
Total Pages: 310
Release: 2011-01-27
Genre: Technology & Engineering
ISBN: 9048195918

Design and optimization of integrated circuits are essential to the creation of new semiconductor chips, and physical optimizations are becoming more prominent as a result of semiconductor scaling. Modern chip design has become so complex that it is largely performed by specialized software, which is frequently updated to address advances in semiconductor technologies and increased problem complexities. A user of such software needs a high-level understanding of the underlying mathematical models and algorithms. On the other hand, a developer of such software must have a keen understanding of computer science aspects, including algorithmic performance bottlenecks and how various algorithms operate and interact. "VLSI Physical Design: From Graph Partitioning to Timing Closure" introduces and compares algorithms that are used during the physical design phase of integrated-circuit design, wherein a geometric chip layout is produced starting from an abstract circuit design. The emphasis is on essential and fundamental techniques, ranging from hypergraph partitioning and circuit placement to timing closure.

Routing Congestion in VLSI Circuits

Routing Congestion in VLSI Circuits
Author: Prashant Saxena
Publisher: Springer Science & Business Media
Total Pages: 254
Release: 2007-04-27
Genre: Technology & Engineering
ISBN: 0387485503

This volume provides a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, offers techniques for estimating and relieving congestion, and provides a critical analysis of the accuracy and effectiveness of these techniques. The book includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow. The subjects covered include an explanation of why the problem of congestion is important and how it will trend, plus definitions of metrics that are appropriate for measuring congestion, and descriptions of techniques for estimating and optimizing routing congestion issues in cell-/library-based VLSI circuits.

Algorithmic Aspects of VLSI Layout

Algorithmic Aspects of VLSI Layout
Author: Majid Sarrafzadeh
Publisher: World Scientific
Total Pages: 411
Release: 1993
Genre: Technology & Engineering
ISBN: 981021488X

In the past two decades, research in VLSI physical design has been directed toward automation of layout process. Since the cost of fabricating a circuit is a fast growing function of the circuit area, circuit layout techniques are developed with an aim to produce layouts with small areas. Other criteria of optimality such as delay and via minimization need to be taken into consideration. This book includes 14 articles that deal with various stages of the VLSI layout problem. It covers topics including partitioning, floorplanning, placement, global routing, detailed routing and layout verification. Some of the chapters are review articles, giving the state-of-the-art of the problems related to timing driven placement, global and detailed routing, and circuit partitioning. The rest of the book contains research articles, giving recent findings of new approaches to the above-mentioned problems. They are all written by leading experts in the field. This book will serve as good references for both researchers and professionals who work in this field.

Algorithms for VLSI Physical Design Automation

Algorithms for VLSI Physical Design Automation
Author: Naveed A. Sherwani
Publisher: Springer Science & Business Media
Total Pages: 554
Release: 2012-12-06
Genre: Technology & Engineering
ISBN: 1461523516

Algorithms for VLSI Physical Design Automation, Second Edition is a core reference text for graduate students and CAD professionals. Based on the very successful First Edition, it provides a comprehensive treatment of the principles and algorithms of VLSI physical design, presenting the concepts and algorithms in an intuitive manner. Each chapter contains 3-4 algorithms that are discussed in detail. Additional algorithms are presented in a somewhat shorter format. References to advanced algorithms are presented at the end of each chapter. Algorithms for VLSI Physical Design Automation covers all aspects of physical design. In 1992, when the First Edition was published, the largest available microprocessor had one million transistors and was fabricated using three metal layers. Now we process with six metal layers, fabricating 15 million transistors on a chip. Designs are moving to the 500-700 MHz frequency goal. These stunning developments have significantly altered the VLSI field: over-the-cell routing and early floorplanning have come to occupy a central place in the physical design flow. This Second Edition introduces a realistic picture to the reader, exposing the concerns facing the VLSI industry, while maintaining the theoretical flavor of the First Edition. New material has been added to all chapters, new sections have been added to most chapters, and a few chapters have been completely rewritten. The textual material is supplemented and clarified by many helpful figures. Audience: An invaluable reference for professionals in layout, design automation and physical design.

VLSI Physical Design Automation

VLSI Physical Design Automation
Author: Sadiq M. Sait
Publisher: World Scientific
Total Pages: 506
Release: 1999
Genre: Technology & Engineering
ISBN: 9789810238834

&Quot;VLSI Physical Design Automation: Theory and Practice is an essential introduction for senior undergraduates, postgraduates and anyone starting work in the field of CAD for VLSI. It covers all aspects of physical design, together with such related areas as automatic cell generation, silicon compilation, layout editors and compaction. A problem-solving approach is adopted and each solution is illustrated with examples. Each topic is treated in a standard format: Problem Definition, Cost Functions and Constraints, Possible Approaches and Latest Developments."--BOOK JACKET.

Logic Synthesis

Logic Synthesis
Author: Srinivas Devadas
Publisher: McGraw-Hill Professional Publishing
Total Pages: 0
Release: 1994
Genre: Computer-aided design
ISBN: 9780070165007

Logic synthesis enables VSLI designers to rapidly lay out the millions of transistors and interconnecting wires that form the circuitry on modern chips, without having to plot each individual logic circuit.

Practical Problems in VLSI Physical Design Automation

Practical Problems in VLSI Physical Design Automation
Author: Sung Kyu Lim
Publisher: Springer Science & Business Media
Total Pages: 292
Release: 2008-07-31
Genre: Technology & Engineering
ISBN: 1402066279

Practical Problems in VLSI Physical Design Automation contains problems and solutions related to various well-known algorithms used in VLSI physical design automation. Dr. Lim believes that the best way to learn new algorithms is to walk through a small example by hand. This knowledge will greatly help understand, analyze, and improve some of the well-known algorithms. The author has designed and taught a graduate-level course on physical CAD for VLSI at Georgia Tech. Over the years he has written his homework with such a focus and has maintained typeset version of the solutions.

Microfluidic Very Large Scale Integration (VLSI)

Microfluidic Very Large Scale Integration (VLSI)
Author: Paul Pop
Publisher: Springer
Total Pages: 277
Release: 2016-02-08
Genre: Technology & Engineering
ISBN: 3319295993

This book presents the state-of-the-art techniques for the modeling, simulation, testing, compilation and physical synthesis of mVLSI biochips. The authors describe a top-down modeling and synthesis methodology for the mVLSI biochips, inspired by microelectronics VLSI methodologies. They introduce a modeling framework for the components and the biochip architecture, and a high-level microfluidic protocol language. Coverage includes a topology graph-based model for the biochip architecture, and a sequencing graph to model for biochemical application, showing how the application model can be obtained from the protocol language. The techniques described facilitate programmability and automation, enabling developers in the emerging, large biochip market.

Introduction to Place and Route Design in VLSIs

Introduction to Place and Route Design in VLSIs
Author: Patrick Lee
Publisher: Lulu.com
Total Pages: 238
Release: 2007-01-05
Genre: Technology & Engineering
ISBN: 1430304928

The book is organized in seven chapters. Physical design flow. Timing constraints. Place and route concepts. Tool vendors. Process constraints. Timing closure. Place and route methodology and flow. ECO and spare gates. Formal verification. Coupling noise. Chip optimization and tapeout.