Vco Based Adcs For Low Power Precision Sensor Interfaces
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| Author | : Jiannan Huang |
| Publisher | : |
| Total Pages | : 104 |
| Release | : 2021 |
| Genre | : |
| ISBN | : |
VCO-based ADCs has long existed as an alternative way of digitization of analog signal. Thanks to its time-domain operation, VCO-based structures using phase domain signal processing have become very promising in highly scaled CMOS processes. The general idea is that since voltage-domain quantization is increasingly difficult to do well in scaled CMOS processes with low supply voltages, it is potentially a better idea to exploit what scaled CMOS processes are very good at: having lots of small transistors that switch fast. Thus, translating input voltage variations to a corresponding phase/frequency variation puts information into the time domain, which can be easily quantized via simple digital circuitry. On the other hand, one well known issue of VCOs is the non-linear voltage-to-frequency transfer characteristic, particularly when input amplitude is large. The distorted frequency output ultimately translates to a distorted digital output, which limits the maximal achievable spurious free dynamic range of the ADC. This dissertation presents a new architecture for VCO-based ADCs called differential pulse code modulation (DPCM) that virtually eliminates the VCO V-to-F nonlinearity by substantially reducing the signal amplitude that the VCO sees so that the VCO operates in the small signal linear region. By using this technique along with other calibration and circuit schemes, three prototype ICs (in which two are for bio-signal and one for audio signal) were fabricated and measured. They all achieved significantly better linearity not only amongst VCO-based ADCs, but also free of any measurable distortions in the output spectra, thus enabling a virtually distortion-less VCO-based ADCs suitable for high dynamic range precision sensing applications.
| Author | : Zhiheng Cao |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 95 |
| Release | : 2008-07-15 |
| Genre | : Technology & Engineering |
| ISBN | : 1402084501 |
Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input. 2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can be a drop-in replacement for existing flash ADCs since it does require any post-processing or calibration step and has the same latency as flash. 3) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for >2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for generating sampling clock to the SAR ADC. A new loop filter structure enables phase error preamplification to lower PLL in-band noise without increasing loop filter capacitor size.
| Author | : Chia-Hung Chen |
| Publisher | : John Wiley & Sons |
| Total Pages | : 164 |
| Release | : 2023-12-19 |
| Genre | : Technology & Engineering |
| ISBN | : 1394178387 |
Comprehensive resource discussing operating principles, available architectures, and design of micropower incremental analog-to-digital converters (IADCs) Incremental Data Converters for Sensor Interfaces describes the motivation for using incremental analog-to-digital converters (IADCs), including the theoretical foundations of their operation, the trade-offs in their use, and the practical issues in the circuit analysis and design of IADCs. The text covers core foundational knowledge such as the key algorithms used, circuits for single-stage and multi-stage IADCs, the design of the digital post filters for single- and multi-stage IADCs, IADC applications in measurement and instrumentation, medicine, imagers, and IoT, and comparison of delta-sigma (D-S) and incremental ADCs (IADCs) in terms of accuracy, latency, and multiplexed operation. To aid in reader comprehension and serve as an excellent classroom learning resource, Incremental Data Converters for Sensor Interfaces includes in-text problems and homework for graduate studies, along with helpful computer codes in MATLAB and Simulink. Additional topics covered in Incremental Data Converters for Sensor Interfaces include: Sensors and sensor interfaces, mixed-mode (analog–digital) communication and consumer signal chains, and ADC algorithms Quantization errors vs. quantization noise, and performance parameters and figures of merit, including resolution, linearity, accuracy, bandwidth, latency, and power dissipation Nyquist-rate and oversampling data converters, noise-shaping ADCs, and basic architectures for IADCs, including single- and multi-stage designs and discrete vs. continuous-time operation Loop filter design, D/A converter design, dynamic element matching and digital calibration, and quantizer design With comprehensive coverage of foundational knowledge surrounding the subject, various real-world examples, and helpful learning aids, Incremental Data Converters for Sensor Interfaces is an essential resource for graduate students in electronics programs, along with industrial circuit design professionals.
| Author | : Samantha Yoder |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 64 |
| Release | : 2011-08-28 |
| Genre | : Technology & Engineering |
| ISBN | : 1441997229 |
This book introduces the concept of voltage-controlled-oscillator (VCO)-based analog-to-digital converters (ADCs). Detailed explanation is given of this promising new class of high resolution and low power ADCs, which use time quantization as opposed to traditional analog-based (i.e. voltage) ADCs.
| Author | : Georges Gielen |
| Publisher | : Springer Nature |
| Total Pages | : 118 |
| Release | : 2022-03-01 |
| Genre | : Technology & Engineering |
| ISBN | : 3030880672 |
This book demonstrates why highly-digital CMOS time-encoding analog-to-digital converters incorporating voltage-controlled oscillators (VCOs) and time-to-digital converters (TDCs) are a good alternative to traditional switched-capacitor S-D modulators for power-efficient sensor, biomedical and communications applications. The authors describe the theoretical foundations and design methodology of such time-based ADCs from the basics to the latest developments. While most analog designers might notice some resemblance to PLL design, the book clearly highlights the differences to standard PLL circuit design and illustrates the design methodology with practical circuit design examples. Describes in detail the design methodology for CMOS time-encoding analog-to-digital converters that can be integrated along with digital logic in a nanometer System on Chip; Assists analog designers with the necessary change in design paradigm, highlighting differences between designing time-based ADCs and traditional analog circuits like switched-capacitor converters and PLLs; Uses a highly-visual, tutorial approach to the topic, including many practical examples of techniques introduced.
| Author | : 陳建良 |
| Publisher | : |
| Total Pages | : 0 |
| Release | : 2022 |
| Genre | : |
| ISBN | : |
| Author | : Taimur Rabuske |
| Publisher | : Springer |
| Total Pages | : 173 |
| Release | : 2016-08-02 |
| Genre | : Technology & Engineering |
| ISBN | : 3319396242 |
This book introduces readers to the potential of charge-sharing (CS) successive approximation register (SAR) analog-to-digital converters (ADCs), while providing extensive analysis of the factors that limit the performance of the CS topology. The authors present guidelines and useful techniques for mitigating the limitations of the architecture, while focusing on the implementation under restricted power budgets and voltage supplies.
| Author | : Sudhanva Madhava Murthy Vasishta |
| Publisher | : |
| Total Pages | : 0 |
| Release | : 2022 |
| Genre | : |
| ISBN | : |
Precision sensor systems require low-noise analog front-end and low-power analog-to-digital converters (ADCs) for processing. To lower power, scaled CMOS technologies use reduced supply voltages which limit the headroom and Signal-to-Noise ratio (SNR), but avails high-resolution clock and time-based circuits to represent analog signals, which makes analog to digital conversion in time-domain more convenient than voltage-domain. This thesis presents a new continuous-time open-loop time-domain Sigma Delta (S-D) ADC architecture with a current input and a capacitor to integrate it linearly. Due to the shortage of headroom in scaled CMOS, the integral is folded at two precisely controlled voltage levels in opposite direction forming a triangular waveform. This offers linear integration with the integral represented partially in digital (Digital Output) and partially in analog (Quantization error) allowing several energy-efficient techniques to finer approximate the error, enhancing the resolution of the ADC including, • Finerflash: Adding and detecting finer voltage levels within the triangle (multi-bit quantization) at the sampling instant. Prototype ICs fabricated in TSMC 180nm CMOS achieved FoM [subscript W] of 1104 fJ/step and FoM [subscript S,DR] of 161 dB. • Subranging: Running the ICO at nominally lower frequency for most of the sampling period and increasing its frequency close to the sampling instant allows to simultaneously achieve high resolution and low power consumption. Prototype ICs fabricated in TSMC 180nm CMOS achieved FoM [subscript W] of 675 fJ/step and FoM [subscript S,DR] of 166 dB. The performance of the prototype ICs is comparable to the state-of-the-art ADCs for low-bandwidth applications in terms of power and figure-of-merit. In addition, the simplicity of implementation of this new architecture opens up a new design arena for high-performance ADCs in shorter channel technologies. The latter part of this thesis presents the demonstration of low-noise analog front-end circuits using a novel symmetric dual-gate MoS2 transistor. A study on the effect of symmetry of the two gates on the I-V characteristics is made. A chopper amplifier with a single MoS2 transistor is realized using a single transistor to frequency translate the low-bandwidth input signal to get the signal away from the noise corner with a nominal gain factor
| Author | : Praveen Prabha |
| Publisher | : |
| Total Pages | : 45 |
| Release | : 2014 |
| Genre | : Analog-to-digital converters |
| ISBN | : |
Sensors find a variety of applications in portable electronics, automotive and biomedical solutions. The demand for low power and high dynamic range makes the design of digital sensor readout circuits quite challenging. Traditionally, these circuits are realized using amplifiers with passive feedback or precision analog comparators which are power hungry and not amenable to technology scaling. This thesis presents design techniques for a low power, amplifier-free, digital sensor current readout circuit. It is realized using an implicit passive integrator, VCO-based quantizer, and mostly digital circuits. A digital IIR filter is used to increase the loop gain and bias the sensor accurately across a wide range of values. Fabricated in a 0.18[micro]m CMOS process, the prototype readout circuit achieves 900pA accuracy over an input current range of 4[micro]A, consumes a total of 77.8[micro]A current, and occupies an active area of 0.36mm2.
| Author | : Viet Nguyen |
| Publisher | : |
| Total Pages | : 0 |
| Release | : 2022 |
| Genre | : |
| ISBN | : |
