Timing Verification And Synthesis Of Circuits For Delay Fault Testability
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Author | : Kaushik Roy |
Publisher | : |
Total Pages | : 240 |
Release | : 1990 |
Genre | : |
ISBN | : |
This thesis concerns the problem of timing verification and synthesis of circuits for robust delay fault testability. The timing verification algorithm uses Register Transfer Level (RTL) descriptions to eliminate false paths (non-sensitizable) due to redundancy, reconvergent fanout, and control signal constraints. The RTL descriptions help to prune the search space because only valid paths are considered. The critical paths obtained from the timing verifier have to be tested for any delay faults. To make the robust delay test generation easier, multilevel combinational logic circuits are synthesized for delay fault testability. Given a multilevel description of a combinational logic circuit, blocked or dependent paths may be present. Blocked or dependent paths due to reconvergent fanout can destroy robustness of tests. A set of path segments called essential paths is checked for blockage or dependency, and a local transformation enhances the delay fault testability of the circuit. It has been shown that a robust delay test can be obtained as a by-product of the logic synthesis procedure.
Author | : Mukund Sivaraman |
Publisher | : Springer Science & Business Media |
Total Pages | : 164 |
Release | : 2012-09-17 |
Genre | : Technology & Engineering |
ISBN | : 1441985786 |
Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Research in (pre-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.
Author | : Bhanu Kapoor |
Publisher | : |
Total Pages | : 206 |
Release | : 1994 |
Genre | : |
ISBN | : |
Author | : Luciano Lavagno |
Publisher | : Springer Science & Business Media |
Total Pages | : 353 |
Release | : 2012-12-06 |
Genre | : Technology & Engineering |
ISBN | : 1461532124 |
Since the second half of the 1980s asynchronous circuits have been the subject of a great deal of research following a period of relative oblivion. The lack of interest in asynchronous techniques was motivated by the progressive shift towards synchronous design techniques that had much more structure and were much easier to verify and synthesize. System design requirements made it impossible to eliminate totally the use of asynchronous circuits. Given the objective difficulty encountered by designers, the asynchronous components of electronic systems such as interfaces became a serious bottleneck in the design process. The use of new models and some theoretical breakthroughs made it possible to develop asynchronous design techniques that were reliable and effective. This book describes a variety of mathematical models and of algorithms that form the backbone and the body of a new design methodology for asyn chronous design. The book is intended for asynchronous hardware designers, for computer-aided tool experts, and for digital designers interested in ex ploring the possibility of designing asynchronous circuits. It requires a solid mathematical background in discrete event systems and algorithms. While the book has not been written as a textbook, nevertheless it could be used as a reference book in an advanced course in logic synthesis or asynchronous design.
Author | : Srinivas Devadas |
Publisher | : |
Total Pages | : 9 |
Release | : 1990 |
Genre | : |
ISBN | : |
Author | : William K.C. Lam |
Publisher | : Springer Science & Business Media |
Total Pages | : 290 |
Release | : 2012-12-06 |
Genre | : Technology & Engineering |
ISBN | : 1461526884 |
Timing research in high performance VLSI systems has advanced at a steady pace over the last few years, while tools, especially theoretical mechanisms, lag behind. Much present timing research relies heavily on timing diagrams, which, although intuitive, are inadequate for analysis of large designs with many parameters. Further, timing diagrams offer only approximations, not exact solutions, to many timing problems and provide little insight in the cases where temporal properties of a design interact intricately with the design's logical functionalities. This book presents a methodology for timing research which facilitates analy sis and design of circuits and systems in a unified temporal and logical domain. In the first part, we introduce an algebraic representation formalism, Timed Boolean Functions (TBF's), which integrates both logical and timing informa tion of digital circuits and systems into a single formalism. We also give a canonical form, TBF BDD's, for them, which can be used for efficient ma nipulation. In the second part, we apply Timed Boolean Functions to three problems in timing research, for which exact solutions are obtained for the first time: 1. computing the exact delays of combinational circuits and the minimum cycle times of finite state machines, 2. analysis and synthesis of wavepipelining circuits, a high speed architecture for which precise timing relations between signals are essential for correct operations, 3. verification of circuit and system performance and coverage of delay faults by testing.
Author | : VLSI Society of India |
Publisher | : Institute of Electrical & Electronics Engineers(IEEE) |
Total Pages | : 626 |
Release | : 1997 |
Genre | : Computers |
ISBN | : 9780818682247 |
Areas covered in this work include: physical design; synthesis; delay test and timing; high-level synthesis; hardware/software co-design; low-power design; verification; VLSI synthesis; testability enhancement; asynchronous design; diagnosis; test and fault modelling; and mixed-signal design.
Author | : Andreas Kuehlmann |
Publisher | : Springer Science & Business Media |
Total Pages | : 699 |
Release | : 2012-12-06 |
Genre | : Computers |
ISBN | : 1461502926 |
In 2002, the International Conference on Computer Aided Design (ICCAD) celebrates its 20th anniversary. This book commemorates contributions made by ICCAD to the broad field of design automation during that time. The foundation of ICCAD in 1982 coincided with the growth of Large Scale Integration. The sharply increased functionality of board-level circuits led to a major demand for more powerful Electronic Design Automation (EDA) tools. At the same time, LSI grew quickly and advanced circuit integration became widely avail able. This, in turn, required new tools, using sophisticated modeling, analysis and optimization algorithms in order to manage the evermore complex design processes. Not surprisingly, during the same period, a number of start-up com panies began to commercialize EDA solutions, complementing various existing in-house efforts. The overall increased interest in Design Automation (DA) re quired a new forum for the emerging community of EDA professionals; one which would be focused on the publication of high-quality research results and provide a structure for the exchange of ideas on a broad scale. Many of the original ICCAD volunteers were also members of CANDE (Computer-Aided Network Design), a workshop of the IEEE Circuits and Sys tem Society. In fact, it was at a CANDE workshop that Bill McCalla suggested the creation of a conference for the EDA professional. (Bill later developed the name).
Author | : Luciano Lavagno |
Publisher | : |
Total Pages | : 656 |
Release | : 1992 |
Genre | : |
ISBN | : |
Author | : Alain Finkel |
Publisher | : Springer Science & Business Media |
Total Pages | : 644 |
Release | : 1992-02-04 |
Genre | : Computers |
ISBN | : 9783540552109 |
This volume gives the proceedings of the ninth Symposium on Theoretical Aspects of Computer Science (STACS). This annual symposium is held alternately in France and Germany and is organized jointly by the Special Interest Group for Fundamental Computer Science of the Association Francaise des Sciences et Technologies de l'Information et des Syst mes (AFCET) and the Special Interest Group for Theoretical Computer Science of the Gesellschaft f}r Informatik (GI). The volume includes three invited lectures and sections on parallel algorithms, logic and semantics, computational geometry, automata and languages, structural complexity, computational geometry and learning theory, complexity and communication, distributed systems, complexity, algorithms, cryptography, VLSI, words and rewriting, and systems.