Time And Statistical Information Utilization In High Efficiency Sub Micron Cmos Successive Approximation Analog To Digital Converters
Download Time And Statistical Information Utilization In High Efficiency Sub Micron Cmos Successive Approximation Analog To Digital Converters full books in PDF, epub, and Kindle. Read online free Time And Statistical Information Utilization In High Efficiency Sub Micron Cmos Successive Approximation Analog To Digital Converters ebook anywhere anytime directly on your device. Fast Download speed and no annoying ads. We cannot guarantee that every ebooks is available!
| Author | : Jon Guerber |
| Publisher | : |
| Total Pages | : 167 |
| Release | : 2013 |
| Genre | : Analog-to-digital converters |
| ISBN | : |
In an industrial and consumer electronic marketplace that is increasingly demanding greater real-world interactivity in portable and distributed devices, analog to digital converter efficiency and performance is being carefully examined. The successive approximation (SAR) analog to digital converter (ADC) architecture has become popular for its high efficiency at mid-speed and resolution requirements. This is due to the one core single bit quantizer, lack of residue amplification, and large digital domain processing allowing for easy process scaling. This work examines the traditional binary capacitive SAR ADC time and statistical information and proposes new structures that optimize ADC performance. The Ternary SAR (TSAR) uses the quantizer delay information to enhance accuracy, speed and power consumption of the overall SAR while providing multi-level redundancy. The early reset merged capacitor switching SAR (EMCS) identifies lost information in the SAR subtraction and optimizes a full binary quanitzer structure for a Ternary MCS DAC. Residue Shaping is demonstrated in SAR and pipeline configurations to allow for an extra bit of signal to noise quantization ratio (SQNR) due to multi-level redundancy. The feedback initialized ternary SAR (FITSAR) is proposed which splits a TSAR into separate binary and ternary sub-ADC structures for speed and power benefits with an inter-stage encoding that not only maintains residue shaping across the binary SAR, but allows for nearly optimally minimal energy consumption for capacitive ternary DACs. Finally, the ternary SAR ideas are applied to R2R DACs to reduce power consumption. These ideas are tested both in simulation and with prototype results.
| Author | : Amir Zjajo |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 311 |
| Release | : 2010-10-29 |
| Genre | : Technology & Engineering |
| ISBN | : 9048197252 |
With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power, low-voltage A/D converters that can be realized in a mainstream deep-submicron CMOS technology. However, the discrepancies between lithography wavelengths and circuit feature sizes are increasing. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. The inherent randomness of materials used in fabrication at nanoscopic scales means that performance will be increasingly variable, not only from die-to-die but also within each individual die. Parametric variability will be compounded by degradation in nanoscale integrated circuits resulting in instability of parameters over time, eventually leading to the development of faults. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. In an attempt to address these issues, Low-Power High-Resolution Analog-to-Digital Converters specifically focus on: i) improving the power efficiency for the high-speed, and low spurious spectral A/D conversion performance by exploring the potential of low-voltage analog design and calibration techniques, respectively, and ii) development of circuit techniques and algorithms to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover errors continuously. The feasibility of the described methods has been verified by measurements from the silicon prototypes fabricated in standard 180nm, 90nm and 65nm CMOS technology.
| Author | : Angel Rodríguez-Vázquez |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 644 |
| Release | : 2004-01-31 |
| Genre | : Technology & Engineering |
| ISBN | : 9781402075469 |
CMOS Telecom Data Converters compiles the latest achievements regarding the design of high-speed and high-resolution data converters in deep submicron CMOS technologies. The four types of analog-to-digital converter architectures commonly found in this arena are covered, namely sigma-delta, pipeline, folding/interpolating and flash. For all these types, latest achievements regarding the solution of critical architectural and circuital issues are presented, and illustrated through IC prototypes with measured state-of-the-art performances. Some of these prototypes are conceived to be employed at the chipset of newest generation wireline modems (ADSL and ADSL+). Others are intended for wireless transceivers. Besides analog-to-digital converters, the book also covers other functions needed for communication systems, such as digital-to-analog converters, analog filters, programmable gain amplifiers, digital filters, and line drivers.
| Author | : Yue Hu |
| Publisher | : |
| Total Pages | : 100 |
| Release | : 2014 |
| Genre | : Analog-to-digital converters |
| ISBN | : |
Time-domain data conversion has recently drawn increased research attention for its highly digital nature in favor of process technology scaling. Also, as the time information being carried by binary voltage, time-domain operation is much less sensitive to voltage noise compared to conventional voltage domain operation. However, for analog-to-digital converter (ADC) application, the challenge lies in the methodology of benefiting from time-domain operation while maintaining/improving the overall data conversion accuracy and power efficiency. This dissertation has a focus on the investigation of novel data conversion topologies based on classic voltage domain operation that is capable of generating time information, to improve ADC resolution, system stability and speed without power penalty. In the first approach, a novel continuous-time (CT) delta-sigma modulator (DSM) using a time-interleaved quantizer is proposed and implemented. Along with the doubled sample rate, the proposed architecture utilizes time information to perform correlated coupling between the two quantizer channels. A 120MS/s CT [delta sigma] ADC using proposed technique is implemented in 0.18 [micro]m CMOS process. The measurement results achieve second order noise coupling from the interleaved quantizer itself without extra phases. More importantly, excess loop delay of two full sample clocks is compensated by time-domain signal coupling; the resulted CT DSM is fully stabilized in 120MHz sampling rate and achieves 11 effective number of bits (ENOB). In the second approach, a new category of pulse-width-modulation (PWM) scheme is proposed and described: time symmetric PWM (TSPWM). An ADC structure is further proposed and implemented utilizing this novel voltage-to-time converter, followed by a first order noise-shaped switched-ring-oscillator (SRO) TDC quantizer. This ADC topology takes advantage of the TDC speed scaling for its digitized operation to boost the overall ADC resolution and signal bandwidth, while the voltage-to-time front-end is able to remain at a much lower speed than the TDC, thanks to the proposed technique. This is the first work that decouples the PWM modulation rate from TDC quantizing speed without distortion penalty. Built in 0.18 [micro]m, the implemented ADC is able to sample at a range from 20MHz to 40MHz, the generated pulse train is quantized by the following SRO TDC at a rate of 400MHz. The prototype chip shows a SFDR improvement over 24dB on the ADC output when TSPWM is used.
| Author | : |
| Publisher | : |
| Total Pages | : 2264 |
| Release | : 1992 |
| Genre | : Engineering |
| ISBN | : |
Since its creation in 1884, Engineering Index has covered virtually every major engineering innovation from around the world. It serves as the historical record of virtually every major engineering innovation of the 20th century. Recent content is a vital resource for current awareness, new production information, technological forecasting and competitive intelligence. The world?s most comprehensive interdisciplinary engineering database, Engineering Index contains over 10.7 million records. Each year, over 500,000 new abstracts are added from over 5,000 scholarly journals, trade magazines, and conference proceedings. Coverage spans over 175 engineering disciplines from over 80 countries. Updated weekly.
| Author | : Amir Zjajo |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 207 |
| Release | : 2013-11-19 |
| Genre | : Technology & Engineering |
| ISBN | : 9400777817 |
One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key device parameters affecting performance of integrated circuits. The growth of variability can be attributed to multiple factors, including the difficulty of manufacturing control, the emergence of new systematic variation-generating mechanisms, and most importantly, the increase in atomic-scale randomness, where device operation must be described as a stochastic process. In addition to wide-sense stationary stochastic device variability and temperature variation, existence of non-stationary stochastic electrical noise associated with fundamental processes in integrated-circuit devices represents an elementary limit on the performance of electronic circuits. In an attempt to address these issues, Stochastic Process Variation in Deep-Submicron CMOS: Circuits and Algorithms offers unique combination of mathematical treatment of random process variation, electrical noise and temperature and necessary circuit realizations for on-chip monitoring and performance calibration. The associated problems are addressed at various abstraction levels, i.e. circuit level, architecture level and system level. It therefore provides a broad view on the various solutions that have to be used and their possible combination in very effective complementary techniques for both analog/mixed-signal and digital circuits. The feasibility of the described algorithms and built-in circuitry has been verified by measurements from the silicon prototypes fabricated in standard 90 nm and 65 nm CMOS technology.
| Author | : Mikael Gustavsson |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 404 |
| Release | : 2000-01-31 |
| Genre | : Technology & Engineering |
| ISBN | : 079237780X |
CMOS Data Converters for Communications distinguishes itself from other data converter books by emphasizing system-related aspects of the design and frequency-domain measures. It explains in detail how to derive data converter requirements for a given communication system (baseband, passband, and multi-carrier systems). The authors also review CMOS data converter architectures and discuss their suitability for communications. The rest of the book is dedicated to high-performance CMOS data converter architecture and circuit design. Pipelined ADCs, parallel ADCs with an improved passive sampling technique, and oversampling ADCs are the focus for ADC architectures, while current-steering DAC modeling and implementation are the focus for DAC architectures. The principles of the switched-current and the switched-capacitor techniques are reviewed and their applications to crucial functional blocks such as multiplying DACs and integrators are detailed. The book outlines the design of the basic building blocks such as operational amplifiers, comparators, and reference generators with emphasis on the practical aspects. To operate analog circuits at a reduced supply voltage, special circuit techniques are needed. Low-voltage techniques are also discussed in this book. CMOS Data Converters for Communications can be used as a reference book by analog circuit designers to understand the data converter requirements for communication applications. It can also be used by telecommunication system designers to understand the difficulties of certain performance requirements on data converters. It is also an excellent resource to prepare analog students for the new challenges ahead.
| Author | : José M. de la Rosa |
| Publisher | : Wiley-IEEE Press |
| Total Pages | : 426 |
| Release | : 2013-05-06 |
| Genre | : Technology & Engineering |
| ISBN | : 9781119979258 |
A comprehensive overview of Sigma-Delta Analog-to-Digital Converters (ADCs) and a practical guide to their design in nano-scale CMOS for optimal performance. This book presents a systematic and comprehensive compilation of sigma-delta converter operating principles, the new advances in architectures and circuits, design methodologies and practical considerations − going from system-level specifications to silicon integration, packaging and measurements, with emphasis on nanometer CMOS implementation. The book emphasizes practical design issues – from high-level behavioural modelling in MATLAB/SIMULINK, to circuit-level implementation in Cadence Design FrameWork II. As well as being a comprehensive reference to the theory, the book is also unique in that it gives special importance on practical issues, giving a detailed description of the different steps that constitute the whole design flow of sigma-delta ADCs. The book begins with an introductory survey of sigma-delta modulators, their fundamentals architectures and synthesis methods covered in Chapter 1. In Chapter 2, the effect of main circuit error mechanisms is analysed, providing the necessary understanding of the main practical issues affecting the performance of sigma-delta modulators. The knowledge derived from the first two chapters is presented in the book as an essential part of the systematic top-down/bottom-up synthesis methodology of sigma-delta modulators described in Chapter 3, where a time-domain behavioural simulator named SIMSIDES is described and applied to the high-level design and verification of sigma-delta ADCs. Chapter 4 moves farther down from system-level to the circuit and physical level, providing a number of design recommendations and practical recipes to complete the design flow of sigma-delta modulators. To conclude the book, Chapter 5 gives an overview of the state-of-the-art sigma-delta ADCs, which are exhaustively analysed in order to extract practical design guidelines and to identify the incoming trends, design challenges as well as practical solutions proposed by cutting-edge designs. Offers a complete survey of sigma-delta modulator architectures from fundamentals to state-of-the art topologies, considering both switched-capacitor and continuous-time circuit implementations Gives a systematic analysis and practical design guide of sigma-delta modulators, from a top-down/bottom-up perspective, including mathematical models and analytical procedures, behavioural modeling in MATLAB/SIMULINK, macromodeling, and circuit-level implementation in Cadence Design FrameWork II, chip prototyping, and experimental characterization. Systematic compilation of cutting-edge sigma-delta modulators Complete description of SIMSIDES, a time-domain behavioural simulator implemented in MATLAB/SIMULINK Plenty of examples, case studies, and simulation test benches, covering the different stages of the design flow of sigma-delta modulators A number of electronic resources, including SIMSIDES, the statistical data used in the state-of-the-art survey, as well as many design examples and test benches are hosted on a companion website Essential reading for Researchers and electronics engineering practitioners interested in the design of high-performance data converters integrated in nanometer CMOS technologies; mixed-signal designers.
| Author | : Chin-Hsin Lin |
| Publisher | : |
| Total Pages | : 0 |
| Release | : 2012 |
| Genre | : Metal oxide semiconductors, Complementary |
| ISBN | : |
Over the past few decades, the advancement in the deep-submicron CMOS process technology has dramatically improved the performance and functionality of modern System-on-Chips (SoC). However, as the complexity and operational speed of today's SoCs increase, characterizing the timing performance of SoCs is becoming more challenging. Embedded measuring techniques for system characterization are therefore becoming necessities. A Time-to-Digital Converter (TDC) is a device that has been widely used for on-chip time measurements due to its excellent reliability and precision. However, accurate TDCs are few and most implementations are challenging, especially for the time resolution of 10ps and below. In this thesis, a new single-stage Vernier Time-to-Digital Converter (VTDC) has been implemented using 0.13[mu]m IBM CMOS technology, and analyzed using HSPICE simulator in Cadence Analog Design Environment. The single-stage VTDC presented in this work utilizes a dynamic-logic phase detector and a Time Difference Amplifier (TDA). The zero dead-zone characteristic of dynamic-logic phase detector allows for the single-stage VTDC to deliver sub-gate delay time resolution. At the same time, the constant gain TDA further improves the VTDC's resolution by pre-amplifying the input time intervals. The developed single-stage VTDC with TDA has demonstrated a linear measurement characteristic for an input dynamic range from 0 to 100ps with a 2.5ps time resolution.
| Author | : Walt Kester |
| Publisher | : Newnes |
| Total Pages | : 977 |
| Release | : 2005 |
| Genre | : Computers |
| ISBN | : 0750678410 |
This complete update of a classic handbook originally created by Analog Devices and never previously published offers the most complete and up-to-date reference available on data conversion, from the world authority on the subject. It describes in depth the theory behind and the practical design of data conversion circuits. It describes the different architectures used in A/D and D/A converters - including many advances that have been made in this technology in recent years - and provides guidelines on which types are best suited for particular applications. It covers error characterization and testing specifications, essential design information that is difficult to find elsewhere. The book also contains a wealth of practical application circuits for interfacing and supporting A/D and D/A converters within an electronic system. In short, everything an electronics engineer needs to know about data converters can be found in this volume, making it an indispensable reference with broad appeal. The accompanying CD-ROM provides software tools for testing and analyzing data converters as well as a searchable pdf version of the text. * brings together a huge amount of information impossible to locate elsewhere. * many recent advances in converter technology simply aren't covered in any other book. * a must-have design reference for any electronics design engineer or technician
