Power Efficient Analog To Digital Converters Using Both Voltage And Time Domain Information
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| Author | : Taehwan Oh |
| Publisher | : |
| Total Pages | : 87 |
| Release | : 2013 |
| Genre | : Analog-to-digital converters |
| ISBN | : |
As advanced wired and wireless communication systems attempt to achieve higher performance, the demand for high resolution and wide signal bandwidth in their associated ADCs is strongly increased. Recently, time-domain quantization has drawn attention from its scalability in deep submicron CMOS processes. Furthermore, there are several interesting aspects of time-domain quantizer by processing the signal in time rather than only in voltage domain especially for power efficiency. This research focuses on developing a new architecture for power efficient, high resolution ADCs using both voltage and time domain information. As a first approach, a new [delta sigma] ADC based on a noise-shaped two-step integrating quantizer which quantizes the signal in voltage and time domains is presented. Attaining an extra order of noise-shaping from the integrating quantizer, the proposed [delta sigma] ADC manifests a second-order noise-shaping with a first-order loop filter. Furthermore, this quantizer provides an 8b uantization in itself, drastically reducing the oversampling requirement. The proposed ADC also incorporates a new feedback DAC topology that alleviates the feedback DAC complexity of a two-step 8b quantizer. The measured results of the prototype ADC implemented in a 0.13[micro]m CMOS demonstrate peak SNDR of 70.7dB (11.5b ENOB) at 8.1mW power, with an 8x OSR at 80MHz sampling frequency. To further improve ADC performance, a Nyquist ADC based on a time-based pipelined TDC is also proposed as a second approach. In this work, a simple V-T conversion scheme with a cheap low gain amplifier in its first stage and a hybrid time-domain quantization stage based on simple charge pump and capacitive DAC in its backend stages, are also proposed to improve ADC linearity and power efficiency. Using voltage and time domain information, the proposed ADC architecture is beneficial for both resolution and power efficiency, with MSBs resolved in voltage domain and LSBs in time domain. The measured results of the prototype ADC implemented in a 0.13[micro]m CMOS demonstrate peak SNDR of 69.3dB (11.2b ENOB) at 6.38mW power and 70MHz sampling frequency. The FOM is 38.2fJ/conversion-step.
| Author | : Simon Louwsma |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 148 |
| Release | : 2010-09-08 |
| Genre | : Technology & Engineering |
| ISBN | : 9048197163 |
Time-interleaved Analog-to-Digital Converters describes the research performed on low-power time-interleaved ADCs. A detailed theoretical analysis is made of the time-interleaved Track & Hold, since it must be capable of handling signals in the GHz range with little distortion, and minimal power consumption. Timing calibration is not attractive, therefore design techniques are presented which do not require timing calibration. The design of power efficient sub-ADCs is addressed with a theoretical analysis of a successive approximation converter and a pipeline converter. It turns out that the first can consume about 10 times less power than the latter, and this conclusion is supported by literature. Time-interleaved Analog-to-Digital Converters describes the design of a high performance time-interleaved ADC, with much attention for practical design aspects, aiming at both industry and research. Measurements show best-inclass performance with a sample-rate of 1.8 GS/s, 7.9 ENOBs and a power efficiency of 1 pJ/conversion-step.
| Author | : Amir Zjajo |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 311 |
| Release | : 2010-10-29 |
| Genre | : Technology & Engineering |
| ISBN | : 9048197252 |
With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power, low-voltage A/D converters that can be realized in a mainstream deep-submicron CMOS technology. However, the discrepancies between lithography wavelengths and circuit feature sizes are increasing. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. The inherent randomness of materials used in fabrication at nanoscopic scales means that performance will be increasingly variable, not only from die-to-die but also within each individual die. Parametric variability will be compounded by degradation in nanoscale integrated circuits resulting in instability of parameters over time, eventually leading to the development of faults. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. In an attempt to address these issues, Low-Power High-Resolution Analog-to-Digital Converters specifically focus on: i) improving the power efficiency for the high-speed, and low spurious spectral A/D conversion performance by exploring the potential of low-voltage analog design and calibration techniques, respectively, and ii) development of circuit techniques and algorithms to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover errors continuously. The feasibility of the described methods has been verified by measurements from the silicon prototypes fabricated in standard 180nm, 90nm and 65nm CMOS technology.
| Author | : Yue Hu |
| Publisher | : |
| Total Pages | : 100 |
| Release | : 2014 |
| Genre | : Analog-to-digital converters |
| ISBN | : |
Time-domain data conversion has recently drawn increased research attention for its highly digital nature in favor of process technology scaling. Also, as the time information being carried by binary voltage, time-domain operation is much less sensitive to voltage noise compared to conventional voltage domain operation. However, for analog-to-digital converter (ADC) application, the challenge lies in the methodology of benefiting from time-domain operation while maintaining/improving the overall data conversion accuracy and power efficiency. This dissertation has a focus on the investigation of novel data conversion topologies based on classic voltage domain operation that is capable of generating time information, to improve ADC resolution, system stability and speed without power penalty. In the first approach, a novel continuous-time (CT) delta-sigma modulator (DSM) using a time-interleaved quantizer is proposed and implemented. Along with the doubled sample rate, the proposed architecture utilizes time information to perform correlated coupling between the two quantizer channels. A 120MS/s CT [delta sigma] ADC using proposed technique is implemented in 0.18 [micro]m CMOS process. The measurement results achieve second order noise coupling from the interleaved quantizer itself without extra phases. More importantly, excess loop delay of two full sample clocks is compensated by time-domain signal coupling; the resulted CT DSM is fully stabilized in 120MHz sampling rate and achieves 11 effective number of bits (ENOB). In the second approach, a new category of pulse-width-modulation (PWM) scheme is proposed and described: time symmetric PWM (TSPWM). An ADC structure is further proposed and implemented utilizing this novel voltage-to-time converter, followed by a first order noise-shaped switched-ring-oscillator (SRO) TDC quantizer. This ADC topology takes advantage of the TDC speed scaling for its digitized operation to boost the overall ADC resolution and signal bandwidth, while the voltage-to-time front-end is able to remain at a much lower speed than the TDC, thanks to the proposed technique. This is the first work that decouples the PWM modulation rate from TDC quantizing speed without distortion penalty. Built in 0.18 [micro]m, the implemented ADC is able to sample at a range from 20MHz to 40MHz, the generated pulse train is quantized by the following SRO TDC at a rate of 400MHz. The prototype chip shows a SFDR improvement over 24dB on the ADC output when TSPWM is used.
| Author | : Pieter Harpe |
| Publisher | : Springer |
| Total Pages | : 419 |
| Release | : 2014-07-23 |
| Genre | : Technology & Engineering |
| ISBN | : 3319079387 |
This book is based on the 18 tutorials presented during the 23rd workshop on Advances in Analog Circuit Design. Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, serving as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.
| Author | : Michael Figueiredo |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 189 |
| Release | : 2012-08-24 |
| Genre | : Technology & Engineering |
| ISBN | : 146143467X |
This book shows that digitally assisted analog to digital converters are not the only way to cope with poor analog performance caused by technology scaling. It describes various analog design techniques that enhance the area and power efficiency without employing any type of digital calibration circuitry. These techniques consist of self-biasing for PVT enhancement, inverter-based design for improved speed/power ratio, gain-of-two obtained by voltage sum instead of charge redistribution, and current-mode reference shifting instead of voltage reference shifting. Together, these techniques allow enhancing the area and power efficiency of the main building blocks of a multiplying digital-to-analog converter (MDAC) based stage, namely, the flash quantizer, the amplifier, and the switched capacitor network of the MDAC. Complementing the theoretical analyses of the various techniques, a power efficient operational transconductance amplifier is implemented and experimentally characterized. Furthermore, a medium-low resolution reference-free high-speed time-interleaved pipeline ADC employing all mentioned design techniques and circuits is presented, implemented and experimentally characterized. This ADC is said to be reference-free because it precludes any reference voltage, therefore saving power and area, as reference circuits are not necessary. Experimental results demonstrate the potential of the techniques which enabled the implementation of area and power efficient circuits.
| Author | : Stephan Henzler |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 132 |
| Release | : 2010-03-10 |
| Genre | : Technology & Engineering |
| ISBN | : 9048186285 |
Micro-electronics and so integrated circuit design are heavily driven by technology scaling. The main engine of scaling is an increased system performance at reduced manufacturing cost (per system). In most systems digital circuits dominate with respect to die area and functional complexity. Digital building blocks take full - vantage of reduced device geometries in terms of area, power per functionality, and switching speed. On the other hand, analog circuits rely not on the fast transition speed between a few discrete states but fairly on the actual shape of the trans- tor characteristic. Technology scaling continuously degrades these characteristics with respect to analog performance parameters like output resistance or intrinsic gain. Below the 100 nm technology node the design of analog and mixed-signal circuits becomes perceptibly more dif cult. This is particularly true for low supply voltages near to 1V or below. The result is not only an increased design effort but also a growing power consumption. The area shrinks considerably less than p- dicted by the digital scaling factor. Obviously, both effects are contradictory to the original goal of scaling. However, digital circuits become faster, smaller, and less power hungry. The fast switching transitions reduce the susceptibility to noise, e. g. icker noise in the transistors. There are also a few drawbacks like the generation of power supply noise or the lack of power supply rejection.
| Author | : Xinpeng Xing |
| Publisher | : Springer |
| Total Pages | : 200 |
| Release | : 2017-10-04 |
| Genre | : Technology & Engineering |
| ISBN | : 3319665650 |
This book discusses both architecture- and circuit-level design aspects of voltage-controlled-oscillator (VCO)-based analog-to-digital converters (ADCs), especially focusing on mitigation of VCO nonlinearity and the improvement of power efficiency. It shows readers how to develop power-efficient complementary-metal-oxide-semiconductor (CMOS) ADCs for applications such as LTE, 802.11n, and VDSL2+. The material covered can also be applied to other specifications and technologies. Design of Power-Efficient Highly Digital Analog-to-Digital Converters for Next-Generation Wireless Communication Systems begins with a general introduction to the applications of an ADC in communications systems and the basic concepts of VCO-based ADCs. The text addresses a wide range of converter architectures including open- and closed-loop technologies. Special attention is paid to the replacement of power-hungry analog blocks with VCO-based circuits and to the mitigation of VCO nonline arity. Various MATLAB®/Simulink® models are provided for important circuit nonidealities, allowing designers and researchers to determine the required specifications for the different building blocks that form the systematic integrated-circuit design procedure. Five different VCO-based ADC design examples are presented, introducing innovations at both architecture and circuit levels. Of these designs, the best power efficiency of a high-bandwidth oversampling ADC is achieved in a 40 nm CMOS demonstration. This book is essential reading material for engineers and researchers working on low-power-analog and mixed-signal design and may be used by instructors teaching advanced courses on the subject. It provides a clear overview and comparison of VCO-based ADC architectures and gives the reader insight into the most important circuit imperfections.
| Author | : Sai-Weng Sin |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 147 |
| Release | : 2010-09-29 |
| Genre | : Technology & Engineering |
| ISBN | : 9048197104 |
Analog-to-Digital Converters (ADCs) play an important role in most modern signal processing and wireless communication systems where extensive signal manipulation is necessary to be performed by complicated digital signal processing (DSP) circuitry. This trend also creates the possibility of fabricating all functional blocks of a system in a single chip (System On Chip - SoC), with great reductions in cost, chip area and power consumption. However, this tendency places an increasing challenge, in terms of speed, resolution, power consumption, and noise performance, in the design of the front-end ADC which is usually the bottleneck of the whole system, especially under the unavoidable low supply-voltage imposed by technology scaling, as well as the requirement of battery operated portable devices. Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters will present new techniques tailored for low-voltage and high-speed Switched-Capacitor (SC) ADC with various design-specific considerations.
| Author | : Karama Mohammed AL-Tamimi |
| Publisher | : |
| Total Pages | : 0 |
| Release | : 2021 |
| Genre | : |
| ISBN | : |
This thesis facilitates the design challenges of analog and mixed-signal circuits in deep sub-micron technology. In this regard, the design of two analog multiplication architectures is proposed. The process, voltage, temperature (PVT) effect was implicitly eliminated by compressing/expanding technique. The architectures can be configured to generate division, inverse, scaling and other analog functions. The theoretical analysis has been demonstrated by post-layout extraction results in 0.18μm CMOS. The consumed power is 3μW and 0.7μW for the first and the second design, respectively. The occupied silicon area is 250 μm2. Furthermore, two techniques for VCO-based ADCs are proposed. The first technique tackles the power supply noise (PSN) using the injection locking oscillation (ILO) mechanism. Although the ILO concept has been beneficial for a variety of clock synchronizations, there has not been any design approach that takes advantage of this concept to assist the VCO-based ADC. By injecting the frequency-modulated signal into a replica VCO, within the locking range, the latter VCO frequency will always lock to the injected frequency. By digitizing the phase instead of frequency, a system level cancellation of PSN has been achieved. The design results validate the analysis with 25dB noise rejection improvement compared to the conventional VCO-based ADC. The second design proposed a preweighted technique to alleviate the nonlinearity of voltage to frequency characteristics in VCO-based ADC to achieve higher resolution. In an open loop configuration, this technique modulates the VCO's frequency by spreading binary preweighted versions of the analog input over the VCO delay cells. As a result, each cell in the VCO produces its own corresponding delay. The results in 65m CMOS show that the voltage-to-frequency transfer characteristics is drastically improved with nonlinearity less than 1% over rail-to-rail input swing. For further area minimization, an inverse R-2R front end is proposed. A prototype was fabricated using 65nm CMOS process. It occupies an actives area of 0.03 mm2 and consumes 3.1 mA from 1 V power supply. Measurement results of linearity indicate SFDR and SNDR of 77 and 66.7 dB, respectively, over 5 MHz passband bandwidth which reveals energy less than 0.2 pJ/step in Walden figure-of-merit.
