Performance And Energy Trade Offs For 3d Ic Noc Interconnects And Architectures
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| Author | : James David Coddington |
| Publisher | : |
| Total Pages | : 108 |
| Release | : 2015 |
| Genre | : Networks on a chip |
| ISBN | : |
"With the increased complexity and continual scaling of integrated circuit performance, multi-core chips with dozens, hundreds, even thousands of parallel computing units require high performance interconnects to maximize data throughput and minimize latency and energy consumption. High core counts render bus based interconnects inefficient and lackluster in performance. Networks-on-Chip were introduced to simplify the interconnect design process and maintain a more scalable interconnection architecture. With the continual scaling of feature sizes for smaller and smaller transistors, the global interconnections of planar integrated circuits are consuming higher energy proportional to the rest of the chip power dissipation as well as increasing communication delays. Three-dimensional integrated circuits were introduced to shorten global wire lengths and increase chip connectivity. These 3D ICs bring heat dissipation challenges as the power density increases drastically for each additional chip layer. One of the most popularly researched vertical interconnection technologies is through-silicon vias (TSVs). TSVs require additional manufacturing steps to build but generally have low energy dissipation and good performance. Alternative wireless technologies such as capacitive or inductive coupling do not require additional manufacturing steps and also provide the option of having a liquid cooling layer between planar chips. they are typically much slower and consume more energy than their wired counterparts, however. This work compares the interconnection technologies across several different NoC architectures including a proposed sparse 3D mesh for inductive coupling that increases vertical throughput per link and reduces chip area compared to the other wireless architectures and technologies."--Abstract.
| Author | : Lennart Bamberg |
| Publisher | : Springer Nature |
| Total Pages | : 403 |
| Release | : 2022-06-27 |
| Genre | : Technology & Engineering |
| ISBN | : 3030982297 |
This book describes the first comprehensive approach to the optimization of interconnect architectures in 3D systems on chips (SoCs), specially addressing the challenges and opportunities arising from heterogeneous integration. Readers learn about the physical implications of using heterogeneous 3D technologies for SoC integration, while also learning to maximize the 3D-technology gains, through a physical-effect-aware architecture design. The book provides a deep theoretical background covering all abstraction-levels needed to research and architect tomorrow’s 3D-integrated circuits, an extensive set of optimization methods (for power, performance, area, and yield), as well as an open-source optimization and simulation framework for fast exploration of novel designs.
| Author | : Abbas Sheibanyrad |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 280 |
| Release | : 2010-11-08 |
| Genre | : Technology & Engineering |
| ISBN | : 1441976183 |
This book presents the research challenges that are due to the introduction of the 3rd dimension in chips for researchers and covers the whole architectural design approach for 3D-SoCs. Nowadays the 3D-Integration technologies, 3D-Design techniques, and 3D-Architectures are emerging as interesting, truly hot, broad topics. The present book gathers the recent advances in the whole domain by renowned experts in the field to build a comprehensive and consistent book around the hot topics of three-dimensional architectures and micro-architectures. This book includes contributions from high level international teams working in this field.
| Author | : Dongjin Lee |
| Publisher | : |
| Total Pages | : 132 |
| Release | : 2018 |
| Genre | : Networks on a chip |
| ISBN | : |
High-performance and energy-efficient Network-on-Chip (NoC) architecture is one of the crucial components of the manycore processing platforms. A very promising NoC architecture recently proposed in the literature is the three-dimensional small-world NoC (3D SWNoC). Due to short vertical links in 3D integration and the robustness of small-world networks, the 3D SWNoC architecture outperforms its other 3D counterparts. However, the performance of 3D SWNoC is highly dependent on the placement of the links and associated routers. In this dissertation, we propose a sensitivity-based link placement algorithm (SEN) to optimize the performance of 3D SWNoC. The sensitivity of a link in a NoC measures the importance of the link. The SEN algorithm optimizes the performance of 3D SWNoC by calculating the sensitivities of all the links in the NoC and removing the least important link repeatedly. We compare the performance of SEN algorithm with simulated annealing and machine learning-based optimization algorithm. 3D NoC architectures suffer from high power density and the resultant thermal hotspots leading to functionality and reliability concerns over time. The power consumption and thermal profiles of 3D NoCs can be improved by incorporating a Voltage-Frequency Island (VFI)-based power management and Reciprocal Design Symmetry (RDS)-based floor planning. We undertake a detailed design space exploration for 3D NoC by considering power-thermal-performance trade-offs. We consider a small-world network-enabled 3D NoC in this performance evaluation due to its superior performance and energy-efficiency compared to other existing 3D NoC. For TSV-based systems, high power density and the resultant thermal hotspot remain major concerns from the perspectives of chip functionality and overall reliability. Due to inherent thermal constraints of a TSV-based 3D system, we are unable to fully exploit the benefits offered by the power management methodology. In this context, emergence of monolithic 3D (M3D) integration has opened new possibility of designing ultra-low-power and high-performance circuits and systems. The smaller dimensions of the inter-layer dielectric and monolithic inter-tier vias offer high-density integration, flexibility of partitioning logic blocks across multiple tiers, and significant reduction of total wire-length. We present a comparative performance evaluation of M3D NoCs with respect to their conventional TSV-based counterparts.
| Author | : Jari Nurmi |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 474 |
| Release | : 2004-07-20 |
| Genre | : Computers |
| ISBN | : 9781402078354 |
In Interconnect-centric Design for Advanced SoC and NoC, we have tried to create a comprehensive understanding about on-chip interconnect characteristics, design methodologies, layered views on different abstraction levels and finally about applying the interconnect-centric design in system-on-chip design. Traditionally, on-chip communication design has been done using rather ad-hoc and informal approaches that fail to meet some of the challenges posed by next-generation SOC designs, such as performance and throughput, power and energy, reliability, predictability, synchronization, and management of concurrency. To address these challenges, it is critical to take a global view of the communication problem, and decompose it along lines that make it more tractable. We believe that a layered approach similar to that defined by the communication networks community should also be used for on-chip communication design. The design issues are handled on physical and circuit layer, logic and architecture layer, and from system design methodology and tools point of view. Formal communication modeling and refinement is used to bridge the communication layers, and network-centric modeling of multiprocessor on-chip networks and socket-based design will serve the development of platforms for SoC and NoC integration. Interconnect-centric Design for Advanced SoC and NoC is concluded by two application examples: interconnect and memory organization in SoCs for advanced set-top boxes and TV, and a case study in NoC platform design for more generic applications.
| Author | : Pradheep Khanna Kaliraj |
| Publisher | : |
| Total Pages | : 128 |
| Release | : 2013 |
| Genre | : Networks on a chip |
| ISBN | : |
"Advancements in the field of chip fabrication has facilitated in integrating more number of transistors in a given area which lead to the era of multi-core processors. Interconnect became the bottleneck for the multi-core processors as the number of cores in a chip increased. The traditional bus based architectures, which are currently used in the processors, cannot scale up to support the increasing number of cores in a multi-core chip. Hence, Network-on-Chip (NoC) is the preferred communication backbone for modern multicore chips. However, the multi-hop data transmission using wireline interconnects result in high energy dissipation and latency. Hence, many alternative interconnect technologies have been proposed such as 3D, wireless, and photonic interconnects. These interconnect technologies have their own advantages and disadvantages. Photonic interconnects have emerged as a promising alternative to the conventional metal/dielectric based on-chip wireline interconnects. Several novel architectures have been proposed using photonic waveguides as interconnects, which are capable of reducing the energy dissipation in data transfer significantly. However, the issues of reliability arising due to waveguide losses and adjacent channel crosstalk in photonic waveguides have not received much attention till date. In this paper we propose and evaluate the performance of a photonic NoC architecture designed by segmenting the waveguides into smaller parts to limit the waveguide losses and signal degradation from electro-optic devices. Through detailed system level simulations in this work we compare the performance of the MSB-PNoC with other PNoC architectures proposed in the recent literature and establish its gains over completely electronic mesh based counterparts."--Abstract.
| Author | : Aniket Dilip Mhatre |
| Publisher | : |
| Total Pages | : 124 |
| Release | : 2014 |
| Genre | : Interconnects (Integrated circuit technology) |
| ISBN | : |
"Advancements in the field of chip fabrication led to the integration of a large number of transistors in a small area, giving rise to the multi-core processor era. Massive multi-core processors facilitate innovation and research in the field of healthcare, defense, entertainment, meteorology and many others. Reduction in chip area and increase in the number of on-chip cores is accompanied by power and temperature issues. In high performance multi-core chips, power and heat are predominant constraints. High performance massive multicore systems suffer from thermal hotspots, exacerbating the problem of reliability in deep submicron technologies. High power consumption not only increases the chip temperature but also jeopardizes the integrity of the system. Hence, there is a need to explore holistic power and thermal optimization and management strategies for massive on-chip multi-core environments. In multi-core environments, the communication fabric plays a major role in deciding the efficiency of the system. In multi-core processor chips this communication infrastructure is predominantly a Network-on-Chip (NoC). Tradition NoC designs incorporate planar interconnects as a result these NoCs have long, multi-hop wireline links for data exchange. Due to the presence of multi-hop planar links such NoC architectures fall prey to high latency, significant power dissipation and temperature hotspots. Networks inspired from nature are envisioned as an enabling technology to achieve highly efficient and low power NoC designs. Adopting wireless technology in such architectures enhance their performance. Placement of wireless interconnects (WIs) alters the behavior of the network and hence a random deployment of WIs may not result in a thermally optimal solution. In such scenarios, the WIs being highly efficient would attract high traffic densities resulting in thermal hotspots. Hence, the location and utilization of the wireless links is a key factor in obtaining a thermal optimal highly efficient Network-on-chip. Optimization of the NoC framework alone is incapable of addressing the effects due to the runtime dynamics of the system. Minimal paths solely optimized for performance in the network may lead to excessive utilization of certain NoC components leading to thermal hotspots. Hence, architectural innovation in conjunction with suitable power and thermal management strategies is the key for designing high performance and energy-efficient multicore systems. This work contributes at exploring various wired and wireless NoC architectures that achieve best trade-offs between temperature, performance and energy-efficiency. It further proposes an adaptive routing scheme which factors in the thermal profile of the chip. The proposed routing mechanism dynamically reacts to the thermal profile of the chip and takes measures to avoid thermal hotspots, achieving a thermally efficient dynamically reconfigurable network on chip architecture."--Abstract.
| Author | : Nishad Nerurkar |
| Publisher | : |
| Total Pages | : 144 |
| Release | : 2013 |
| Genre | : Interconnects (Integrated circuit technology) |
| ISBN | : |
"Continued scaling of device geometries according to Moore's Law is enabling complete end-user systems on a single chip. Massive multicore processors are enablers for many information and communication technology (ICT) innovations spanning various domains, including healthcare, defense, and entertainment. In the design of high-performance massive multicore chips, power and heat are dominant constraints. Temperature hotspots witnessed in multicore systems exacerbate the problem of reliability in deep submicron technologies. Hence, there is a great need to explore holistic power and thermal optimization and management strategies for the massive multicore chips. High power consumption not only raises chip temperature and cooling cost, but also decreases chip reliability and performance. thus, addressing thermal concerns at different stages of the design and operation is critical to the success of future generation systems. The performance of a multicore chip is also influenced by its overall communication infrastructure, which is predominantly a Network-on-Chip (NoC). The existing method of implementing a NoC with planar metal interconnects is deficient due to high latency, significant power consumption, and temperature hotspots arising out of long, multi-hop wireline links used in data exchange. On-chip wireless networks are envisioned as an enabling technology to design low power and high bandwidth massive multicore architectures. However, optimizing wireless NoCs for best performance does not necessarily guarantee a thermally optimal interconnection architecture. The wireless links being highly efficient attract very high traffic densities which in turn results in temperature hotspots. Therefore, while the wireless links result in better performance and energy-efficiency, they can also cause temperature hotspots and undermine the reliability of the system. Consequently, the location and utilization of the wireless links is an important factor in thermal optimization of high performance wireless Networks-on-Chip. Architectural innovation in conjunction with suitable power and thermal management strategies is the key for designing high performance yet energy-efficient massive multicore chips. This work contributes to exploration of various design methodologies for establishing wireless NoC architectures that achieve the best trade-offs between temperature, performance and energy-efficiency. It further demonstrates that incorporating Dynamic Thermal Management (DTM) on a multicore chip designed with such temperature and performance optimized Wireless Network-on-Chip architectures improves thermal profile while simultaneously providing lower latency and reduced network energy dissipation compared to its conventional counterparts."--Abstract.
| Author | : Leonard Barolli |
| Publisher | : Springer Nature |
| Total Pages | : 1493 |
| Release | : 2020-03-27 |
| Genre | : Technology & Engineering |
| ISBN | : 3030440419 |
This proceedings book covers the theory, design and applications of computer networks, distributed computing and information systems. Today’s networks are evolving rapidly, and there are several developing areas and applications. These include heterogeneous networking supported by recent technological advances in power wireless communications, along with silicon integration of various functionalities such as sensing, communications, intelligence and actuations, which is emerging as a critically important disruptive computer class based on a new platform, networking structure and interface that enables novel, low-cost and high-volume applications. However, implemeting these applications has sometimes been difficult due to interconnection problems. As such, different networks need to collaborate, and wired and next-generation wireless systems need to be integrated in order to develop high-performance computing solutions to address the problems arising from these networks’ complexities. This ebook presents the latest research findings, as well as theoretical and practical perspectives on the innovative methods and development techniques related to the emerging areas of information networking and applications
| Author | : Opoku Agyeman Michael |
| Publisher | : LAP Lambert Academic Publishing |
| Total Pages | : 180 |
| Release | : 2015-07-13 |
| Genre | : |
| ISBN | : 9783659758133 |
Three dimensional Networks-on-Chip (3D NoCs) have attracted a growing interest to solve on-chip communication demands of future multi-core embedded systems. However, 3D NoCs have not been completely accepted into the mainstream due to issues such as the high cost and complexity of manufacturing 3D vertical wires, larger memory, area and power consumption of 3D NoC components than that of conventional 2D NoC. This thesis aims at optimizing 3D NoCs by modeling and evaluating alternate NoC topologies, routing algorithms and mapping techniques to achieve optimized area, power and performance parameters (latency and throughput). Particularly, novel 3D NoC router architectures and their possible combinations have been investigated with the aim of achieving lower area and power consumption of on-chip communication components with a minimal performance trade-off. This book investigates different heterogeneous 3D NoC architectures which combine 2D and 3D routers to improve area and energy efficiency of 3D NoCs with minimal performance degradation.
