Oblivious Routing Schemes for Multi-processor Networks
Author | : Ian Parberry |
Publisher | : |
Total Pages | : 19 |
Release | : 1985 |
Genre | : Computer networks |
ISBN | : |
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Author | : Ian Parberry |
Publisher | : |
Total Pages | : 19 |
Release | : 1985 |
Genre | : Computer networks |
ISBN | : |
Author | : Stephen Wilson Turner |
Publisher | : |
Total Pages | : 163 |
Release | : 1995 |
Genre | : Computer storage devices |
ISBN | : |
This thesis presents the development and use of a performance analysis methodology suitable for use in the evaluation of multiprocessor interconnection networks. The study is grounded in a detailed evaluation of the Cedar multiprocessor. Using characteristics of the behavior exhibited by the benchmarks studied on that system, a burst-traffic model is developed. The performance predictions of the model for adaptive and oblivious virtual-channel routers used in a 2D torus are compared to those of an open-loop random-traffic model, and significant differences are shown to exist. The design of a novel adaptive router, the Shunt router, is proposed. Proofs of its freedom from deadlock and livelock are provided, showing its suitability for use in the construction of a shared-memory multiprocessor. The burst traffic model is used to drive simple versions of the Shunt router and compare its performance to those of the virtual-channel routers discussed previously. The Shunt router is shown to provide a suitable base for explorations of alterations to the routing algorithms and size of buffers within the router, due to its simplicity of structure. The Shunt router is then augmented with a variety of adaptive routing algorithms. The performance of these algorithms, as well as two oblivious routing algorithms, is evaluated. The results show that structure in oblivious routing is important, and several adaptive routing schemes perform equally well. The Shunt router is also used to evaluate the impact of queue sizes on performance, as well as the interaction between queue lengths and adaptivity. Finally, a traffic-throttling network interface is used, with results that show it is primarily useful in cases of limited router buffering. Analytic performance bounds are developed, and used to place the improvements due to adaptive routing into perspective. These bounds are derived from considerations of the systems topology and the structure of the burst-traffic model. Minimum latency, bisection-width, and a complex mean value analysis model are developed, and each is shown to have utility in different areas of performance prediction and comparison. Given the context of the performance bounds, the adaptive routers are shown to achieve a significant percentage of the potential performance improvement.
Author | : S. S. Iyengar |
Publisher | : MIT Press |
Total Pages | : 175 |
Release | : 2015-05-01 |
Genre | : Computers |
ISBN | : 0262328976 |
Versatile solutions to routing network flows in unpredictable circumstances, presenting both mathematical tools and applications. Our increasingly integrated world relies on networks both physical and virtual to transfer goods and information. The Internet is a network of networks that connects people around the world in a real-time manner, but it can be disrupted by massive data flows, diverse traffic patterns, inadequate infrastructure, and even natural disasters and political conflict. Similar challenges exist for transportation and energy distribution networks. There is an urgent need for intelligent and adaptable routing of network flows, and a rich literature has evolved that treats “oblivious network design.” This book offers novel computational schemes for efficiently solving routing problems in unpredictable circumstances and proposes some real world applications for them. The versatile routing schemes mathematically guarantee long-term efficiency and are most appropriate for networks with non-deterministic (or oblivious) current and past states. After an introduction to network design and the importance of routing problems, the book presents mathematical tools needed to construct versatile routing schemes, emphasizing the role of linked hierarchical data structures, both top-down and bottom-up. It then describes two important applications of versatile routing schemes: a secure model for congestion-free content-centric networks (which will play a key role in the future of the Internet) and a novel approach for the distribution of green power resources on a smart electricity grid.
Author | : Ming-Yang Kao |
Publisher | : Springer Science & Business Media |
Total Pages | : 1200 |
Release | : 2008-08-06 |
Genre | : Computers |
ISBN | : 0387307702 |
One of Springer’s renowned Major Reference Works, this awesome achievement provides a comprehensive set of solutions to important algorithmic problems for students and researchers interested in quickly locating useful information. This first edition of the reference focuses on high-impact solutions from the most recent decade, while later editions will widen the scope of the work. All entries have been written by experts, while links to Internet sites that outline their research work are provided. The entries have all been peer-reviewed. This defining reference is published both in print and on line.
Author | : Kyung Min Su |
Publisher | : |
Total Pages | : 8 |
Release | : 2008 |
Genre | : Computer algorithms |
ISBN | : |
Interconnection networks have been adopted in multicomputer systems, clusters, or chip multiprocessors (CMPs). Among various routing algorithms in interconnection networks, adaptive routing shows the best performance with most traffic types. In this paper, we propose new adaptive routing algorithms considering the remaining hops in addition to local network status. The proposed algorithms make adaptive decisions only when the remaining hops are less than some threshold and congestion is detected, or they do oblivious routing in other cases. As a result, the number of adaptive decisions is greatly reduced. Consequently our proposed algorithms have less adaptive overhead.
Author | : Luc Bouge |
Publisher | : Springer Science & Business Media |
Total Pages | : 886 |
Release | : 1996-08-14 |
Genre | : Computers |
ISBN | : 9783540616269 |
Content Description #Includes bibliographical references and index.
Author | : Emilio Luque |
Publisher | : Springer |
Total Pages | : 991 |
Release | : 2008-08-21 |
Genre | : Computers |
ISBN | : 3540854517 |
This book constitutes the refereed proceedings of the 14th International Conference on Parallel Computing, Euro-Par 2008, held in Las Palmas de Gran Canaria, Spain, in August 2008. The 86 revised papers presented were carefully reviewed and selected from 264 submissions. The papers are organized in topical sections on support tools and environments; performance prediction and evaluation; scheduling and load balancing; high performance architectures and compilers; parallel and distributed databases; grid and cluster computing; peer-to-peer computing; distributed systems and algorithms; parallel and distributed programming; parallel numerical algorithms; distributed and high-performance multimedia; theory and algorithms for parallel computation; and high performance networks.
Author | : Marcello Coppola |
Publisher | : CRC Press |
Total Pages | : 292 |
Release | : 2020-10-14 |
Genre | : Technology & Engineering |
ISBN | : 1420044729 |
Streamlined Design Solutions Specifically for NoC To solve critical network-on-chip (NoC) architecture and design problems related to structure, performance and modularity, engineers generally rely on guidance from the abundance of literature about better-understood system-level interconnection networks. However, on-chip networks present several distinct challenges that require novel and specialized solutions not found in the tried-and-true system-level techniques. A Balanced Analysis of NoC Architecture As the first detailed description of the commercial Spidergon STNoC architecture, Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC examines the highly regarded, cost-cutting technology that is set to replace well-known shared bus architectures, such as STBus, for demanding multiprocessor system-on-chip (SoC) applications. Employing a balanced, well-organized structure, simple teaching methods, numerous illustrations, and easy-to-understand examples, the authors explain: how the SoC and NoC technology works why developers designed it the way they did the system-level design methodology and tools used to configure the Spidergon STNoC architecture differences in cost structure between NoCs and system-level networks From professionals in computer sciences, electrical engineering, and other related fields, to semiconductor vendors and investors – all readers will appreciate the encyclopedic treatment of background NoC information ranging from CMPs to the basics of interconnection networks. The text introduces innovative system-level design methodology and tools for efficient design space exploration and topology selection. It also provides a wealth of key theoretical and practical MPSoC and NoC topics, such as technological deep sub-micron effects, homogeneous and heterogeneous processor architectures, multicore SoC, interconnect processing units, generic NoC components, and embeddings of common communication patterns.
Author | : Kevin Bolding |
Publisher | : Springer Science & Business Media |
Total Pages | : 340 |
Release | : 1994-09-28 |
Genre | : Computers |
ISBN | : 9783540584292 |
This volume contains revised versions of the 23 regular papers presented at the First International Workshop on Parallel Computer Routing and Communication (PCRCW '94), held in Seattle, Washington in May 1994. Routing for parallel computer communication has recently experienced almost explosive activity: ever increasing processor speeds are placing greater demands on interprocessor communication, while technological advances offer new capabilities to respond to those demands. The contributions from industry and academia cover all areas, from details of hardware design to proofs of theoretical results. There are also many papers dealing with the performance of various adaptive routing schemes, new network topologies, network interfaces, and fault-tolerant issues.
Author | : Bryon Moyer |
Publisher | : Newnes |
Total Pages | : 646 |
Release | : 2013-02-27 |
Genre | : Computers |
ISBN | : 0123914612 |
This Expert Guide gives you the techniques and technologies in embedded multicore to optimally design and implement your embedded system. Written by experts with a solutions focus, this encyclopedic reference gives you an indispensable aid to tackling the day-to-day problems when building and managing multicore embedded systems. Following an embedded system design path from start to finish, our team of experts takes you from architecture, through hardware implementation to software programming and debug. With this book you will learn: • What motivates multicore • The architectural options and tradeoffs; when to use what • How to deal with the unique hardware challenges that multicore presents • How to manage the software infrastructure in a multicore environment • How to write effective multicore programs • How to port legacy code into a multicore system and partition legacy software • How to optimize both the system and software • The particular challenges of debugging multicore hardware and software Examples demonstrating timeless implementation details Proven and practical techniques reflecting the authors’ expertise built from years of experience and key advice on tackling critical issues