Modeling And Simulation Of Electrical Overstress Failures In Input Output Protection Devices Of Integrated Circuits
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Author | : Carlos H. Diaz |
Publisher | : Springer Science & Business Media |
Total Pages | : 165 |
Release | : 2012-12-06 |
Genre | : Technology & Engineering |
ISBN | : 1461527880 |
Electrical overstress (EOS) and Electrostatic discharge (ESD) pose one of the most dominant threats to integrated circuits (ICs). These reliability concerns are becoming more serious with the downward scaling of device feature sizes. Modeling of Electrical Overstress in Integrated Circuits presents a comprehensive analysis of EOS/ESD-related failures in I/O protection devices in integrated circuits. The design of I/O protection circuits has been done in a hit-or-miss way due to the lack of systematic analysis tools and concrete design guidelines. In general, the development of on-chip protection structures is a lengthy expensive iterative process that involves tester design, fabrication, testing and redesign. When the technology is changed, the same process has to be repeated almost entirely. This can be attributed to the lack of efficient CAD tools capable of simulating the device behavior up to the onset of failure which is a 3-D electrothermal problem. For these reasons, it is important to develop and use an adequate measure of the EOS robustness of integrated circuits in order to address the on-chip EOS protection issue. Fundamental understanding of the physical phenomena leading to device failures under ESD/EOS events is needed for the development of device models and CAD tools that can efficiently describe the device behavior up to the onset of thermal failure. Modeling of Electrical Overstress in Integrated Circuits is for VLSI designers and reliability engineers, particularly those who are working on the development of EOS/ESD analysis tools. CAD engineers working on development of circuit level and device level electrothermal simulators will also benefit from the material covered. This book will also be of interest to researchers and first and second year graduate students working in semiconductor devices and IC reliability fields.
Author | : E. Ajith Amerasekera |
Publisher | : John Wiley & Sons |
Total Pages | : 434 |
Release | : 2002-05-22 |
Genre | : Technology & Engineering |
ISBN | : |
* Examines the various methods available for circuit protection, including coverage of the newly developed ESD circuit protection schemes for VLSI circuits. * Provides guidance on the implementation of circuit protection measures. * Includes new sections on ESD design rules, layout approaches, package effects, and circuit concepts. * Reviews the new Charged Device Model (CDM) test method and evaluates design requirements necessary for circuit protection.
Author | : Soon Huat Ong |
Publisher | : Institute of Electrical & Electronics Engineers(IEEE) |
Total Pages | : 278 |
Release | : 1995 |
Genre | : Technology & Engineering |
ISBN | : 9780780327979 |
Author | : |
Publisher | : |
Total Pages | : 1008 |
Release | : 1998 |
Genre | : Integrated circuits |
ISBN | : |
Author | : |
Publisher | : |
Total Pages | : 448 |
Release | : 2004 |
Genre | : Electric discharges |
ISBN | : |
Author | : Min Zhang |
Publisher | : |
Total Pages | : 1016 |
Release | : 1998 |
Genre | : Electromechanical devices |
ISBN | : |
Author | : |
Publisher | : |
Total Pages | : 650 |
Release | : 1995 |
Genre | : Semiconductors |
ISBN | : |
Author | : |
Publisher | : |
Total Pages | : 704 |
Release | : 1999 |
Genre | : Dissertations, Academic |
ISBN | : |
Author | : Steven H. Voldman |
Publisher | : John Wiley & Sons |
Total Pages | : 368 |
Release | : 2013-08-27 |
Genre | : Technology & Engineering |
ISBN | : 1118703332 |
Electrical Overstress (EOS) continues to impact semiconductor manufacturing, semiconductor components and systems as technologies scale from micro- to nano-electronics. This bookteaches the fundamentals of electrical overstress and how to minimize and mitigate EOS failures. The text provides a clear picture of EOS phenomena, EOS origins, EOS sources, EOS physics, EOS failure mechanisms, and EOS on-chip and system design. It provides an illuminating insight into the sources of EOS in manufacturing, integration of on-chip, and system level EOS protection networks, followed by examples in specific technologies, circuits, and chips. The book is unique in covering the EOS manufacturing issues from on-chip design and electronic design automation to factory-level EOS program management in today’s modern world. Look inside for extensive coverage on: Fundamentals of electrical overstress, from EOS physics, EOS time scales, safe operating area (SOA), to physical models for EOS phenomena EOS sources in today’s semiconductor manufacturing environment, and EOS program management, handling and EOS auditing processing to avoid EOS failures EOS failures in both semiconductor devices, circuits and system Discussion of how to distinguish between EOS events, and electrostatic discharge (ESD) events (e.g. such as human body model (HBM), charged device model (CDM), cable discharge events (CDM), charged board events (CBE), to system level IEC 61000-4-2 test events) EOS protection on-chip design practices and how they differ from ESD protection networks and solutions Discussion of EOS system level concerns in printed circuit boards (PCB), and manufacturing equipment Examples of EOS issues in state-of-the-art digital, analog and power technologies including CMOS, LDMOS, and BCD EOS design rule checking (DRC), LVS, and ERC electronic design automation (EDA) and how it is distinct from ESD EDA systems EOS testing and qualification techniques, and Practical off-chip ESD protection and system level solutions to provide more robust systems Electrical Overstress (EOS): Devices, Circuits and Systems is a continuation of the author’s series of books on ESD protection. It is an essential reference and a useful insight into the issues that confront modern technology as we enter the nano-electronic era.
Author | : O. Kononchuk |
Publisher | : Elsevier |
Total Pages | : 503 |
Release | : 2014-06-19 |
Genre | : Technology & Engineering |
ISBN | : 0857099256 |
Silicon-On-Insulator (SOI) Technology: Manufacture and Applications covers SOI transistors and circuits, manufacture, and reliability. The book also looks at applications such as memory, power devices, and photonics. The book is divided into two parts; part one covers SOI materials and manufacture, while part two covers SOI devices and applications. The book begins with chapters that introduce techniques for manufacturing SOI wafer technology, the electrical properties of advanced SOI materials, and modeling short-channel SOI semiconductor transistors. Both partially depleted and fully depleted SOI technologies are considered. Chapters 6 and 7 concern junctionless and fin-on-oxide field effect transistors. The challenges of variability and electrostatic discharge in CMOS devices are also addressed. Part two covers recent and established technologies. These include SOI transistors for radio frequency applications, SOI CMOS circuits for ultralow-power applications, and improving device performance by using 3D integration of SOI integrated circuits. Finally, chapters 13 and 14 consider SOI technology for photonic integrated circuits and for micro-electromechanical systems and nano-electromechanical sensors. The extensive coverage provided by Silicon-On-Insulator (SOI) Technology makes the book a central resource for those working in the semiconductor industry, for circuit design engineers, and for academics. It is also important for electrical engineers in the automotive and consumer electronics sectors. - Covers SOI transistors and circuits, as well as manufacturing processes and reliability - Looks at applications such as memory, power devices, and photonics