In recent years, as VLSI technology scales into the nanometer domain, increasingly significant parametric variations and prevalent defects bring an amount of new challenges into VLSI design. Such significant parametric variations and prevalent defects result from manufacturing process limitations, e.g., resolution limitation of lithography processes in manufacturing subwaveform layout features which leads to lateral dimension variations for layout features, and ultimately from the uncertainty principle of quantum physics which leads to variations of vertical dimensions of layout features, dopant concentration, temperature, stress, and so on. The problem is going to be aggravated during aggressive VLSI design further, e.g., with clock frequency, increasing device density, and on-chip temperature which contributes to the increase of parametric variations and defect densities, and with tighter design constraints which increase the vulnerability of VLSI designs to such parametric variations and defects. Performance verification becomes a growing challenge in nanometer-scale VLSI design due to those significant parametric variations and increasingly prevalent catastrophic defects. Such parametric variations and defects induce signal propagation delay variations which may accumulate along a path leading to timing errors at the component level According to quantum physics, these parametric variations cannot be reduced below certain levels at nanometer scale and hence must be handled by new design methods. This dissertation focuses on several emerging problems including dynamic delay test pattern generation and error-resilient design in nanometer-scale VLSI design. Nanometer-scale VLSI systems are subject to increasingly significant parametric variations and prevalent defects. Those parametric variations and prevalent defects result from manufacturing process limitations. The state-of-the-art statistical static delay test technology fails in capturing these dramatic parametric variations. As a result, it provides too pessimistic timing estimate and less accurate performance verification results to evaluate the system properly. In this thesis, we observe that VLSI timing analysis and power estimation targets the same circuit switching activities and signal probability-based statistical technique achieves accurate estimation rate in power estimation field. By leveraging with the existing power estimation techniques, a novel VLSI delay test pattern generation technology is proposed based on signal probability-based statistical timing analysis method. Furthermore, as clock frequency and parametric impedance increase significantly, power and ground supply voltage variation has become another indispensable parameter in dynamic statistical VLSI timing analysis and delay test. Power and ground supply voltage variation refers to the voltage drop or bounce on the supply network. Impacted supply voltage levels degrade cell transitions in a circuit and may cause timing errors when accumulating along paths. Delay test and timing analysis without consideration of such supply voltage variations may induce test escape. Existing delay test techniques considering supply voltage variations mainly focus on maximum supply voltage noise, however, maximum supply voltage noise is not necessarily related to maximum critical path delay. Instead of maximum supply voltage noises, two innovative algorithms are proposed aiming to maximize the impacted critical path delay directly. Besides, power and ground supply voltage variation is input-pattern related. Different input patterns provide different impact on supply voltage variations. Hence, a chicken-egg dilemma is formed between supply voltage noise and input patterns, which requires an iteration process to achieve the final balance scenario. In this thesis, we propose a novel flow of supply voltage variation-aware delay test pattern generation leveraging two proposed algorithms to generate delay test pattern which triggers maximum critical path delay. Finally, the final objective of delay testing is to prevent circuits from timing errors or to detect circuits which have developed faults subsequent to their commitment. Once timing/soft errors occur in the circuit, it would be the best that an error resilient mechanism, e.g. build-in soft error-resilient design technique, handles such errors that the integrity of outputs is guaranteed. As to error-resilient design, we leverage the existing fault-secure logic design techniques, and propose design methodologies for (1) group-sliced logic (GSL) networks with outputs in group distance-two code for guaranteed single soft error resilience, and (2) inversion-free logic (IFL) networks with outputs in delay-insensitive (DI) code, which clears all timing errors and achieves adaptive maximum performance in the absence of external soft errors at a higher area/power cost compared with the existing logic paradigms.