Over the past decade, telecommunication systems have dramatically grown providing services which require ever more data rate with ever more mobility. To sustain this growth, enhanced and new techniques were implemented in ever more optimised digital circuits. A novel approach could be soon necessary for some of these techniques, due to the limitations of their hardware implementations. Error correction is one of them. It allows to reduce the energy used to send information, but, when implemented on a chip, it is a bottleneck in terms of data throughput and of, paradoxically, power consumption. The analogue iterative decoding could solve this problem. This technique, promising high performance, requires new architectures and codes adapted to the constraints of analogue processing to challenge digital circuits in the field of industrial applications. A novel architecture and a novel turbo decoding algorithm, offering a good compromise between onchip area and data rate, are proposed in this thesis. They pave the way for integrating flexible high-speed analogue turbo decoders dealing with different frame lengths ranging from a few dozen to a few thousand bits. The new architecture and decoding algorithm are applied to a DVB-RCS-like code. The component 8-state decoder used in this new architecture was designed for a 0.25μm BiCMOS process. Dealing with frames made up of 24 double-binary symbols, it is, up to this date, one of the most complex analogue decoders ever designed. Implemented on chip, the circuit was successfully tested at 100Mbit/s while consuming 414mW on a 2.8V analogue core supply. It was shown to provide a bit error rate as close as 0.3dB to the digital one.