Abstract: Emerging broadband applications are pushing for the need to build high data rate wireless transceivers at 60GHz for high volume low cost mobile devices. Central to the success of implementing such transceivers is the robust design of 60GHz CMOS RF front ends, especially the low noise amplifiers (LNAs). In the future, CMOS technology is expected to enable low-cost mm-wave applications such as high data-rate communication links, passive and active imaging and sensor systems, and instrumentation and measurements equipment. Building highly integrated inexpensive mm-wave CMOS devices requires high quality factor lumped and distributed passives with accurate and scalable transistor and passives models. My research work focuses on demonstrating a methodology for generating a scalable compact model for on-chip transmission lines and interconnects on lossy silicon substrate. The model is demonstrated over 20-60 GHz frequency band using two types of transmission lines built in TSMC's 0.18 um CMOS technology. Several CPWs and Microstrip lines are designed with different lengths to verify the accuracy and scalability of the extracted model. The compact model shows an excellent agreement with measured data with maximum deviation in S11 magnitude and phase of 9.2% and 5.6%, respectively, and maximum deviation in S21 magnitude and phase of 10.1% and 6.6%, respectively. Compared to existing model extraction methodologies, the required time for generating the compact model and simulating transmission lines is reduced significantly. The generated models are fully compatible with all commercial circuit simulators. This work presents key design techniques for different CMOS mm-wave LNA topologies. The proposed LNA topologies are, the three-stage cascode RF NMOS configuration and four-stage Common Gate followed by Common Source configuration. Simulation results for 60GHz LNAs show that the first topology can achieve a peak gain of 16.67 dB with a 3-dB bandwidth of 7 GHz, and a noise figure less than 11.04 dB over the entire bandwidth. The achieved peak gain from the second topology is 9.7 dB with a 3-dB bandwidth of 7 GHz and a noise figure less than 13.06 dB over the entire bandwidth. Simulation results for Sub-THz LNAs show that the first topology can achieve a peak gain of 23.5 dB at 92.1 GHz with a 3-dB bandwidth of 25 GHz, and a noise figure less than 5.5 dB over the entire bandwidth. The achieved peak gain from the second topology is 23.2 dB at 105 GHz with a 3-dB bandwidth of 15 GHz and a noise figure less than 6.1 dB over the entire bandwidth. The LNAs are designed and tested in 90nm RF CMOS. Moreover in today's radio design environment, the front-end analog devices in the transceiver require several silicon spins before they meet the specifications and they have relatively low yields. My work aims to propose a digital self-calibration technique for LNAs' to enhance the yield to at least 90%. The proposed technique is shown to maintain typical specified performance at worst case corners in the presence of random process, supply and temperature variations, and hence allowing for manufacturable 60GHz RF CMOS design for high volume applications without leading to over-design or increasing power consumption.