Ieee Std 1800 2009 Ieee Standard For Systemverilog Unified Hardware Design Specification And Verification Language
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IEEE Standard for SystemVerilog--unified Hardware Design, Specification, and Verification Language
Author | : IEEE Computer Society. Design Automation Standards Committee |
Publisher | : |
Total Pages | : 1275 |
Release | : 2013 |
Genre | : |
ISBN | : 9780738181103 |
Abstract: The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages. Keywords: assertions, design automation, design verification, hardware description language, HDL, HDVL, IEEE 1800, PLI, programming language interface, SystemVerilog, Verilog, VPI.
1800-2009 IEEE Standard for System Verilog-Unified Hardware Design, Specification, and Verification Language
Author | : |
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Total Pages | : |
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Genre | : Computer hardware description languages |
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