High Speed And Low Power Techniques For Successive Approximation Register Analog To Digital Converters
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| Author | : Eric Lee Swindlehurst |
| Publisher | : |
| Total Pages | : 86 |
| Release | : 2020 |
| Genre | : |
| ISBN | : |
Broadband wireless communication systems demand power-efficient analog-to-digital converters (ADCs) in the GHz and medium resolution regime. While high-speed architectures such as the flash and pipelined ADCs are capable of GHz operations, their high-power consumption reduces their attractiveness for mobile applications. On the other hand, the successive-approximation-register (SAR) ADC has an excellent power efficiency, but its slow speed has traditionally limited it to MHz applications. This dissertation puts forth several novel techniques to significantly increase the speed and power efficiency of the SAR architecture and demonstrates them in a low-power 10-GHz SAR ADC suitable for broadband wireless communications.
| Author | : Ramgopal Sekar |
| Publisher | : |
| Total Pages | : 160 |
| Release | : 2010 |
| Genre | : |
| ISBN | : |
In this work, the author investigated circuit techniques to reduce the power consumption of Successive Approximation Register Analog-to-Digital Converter (SAR-ADC). The author developed four low-power SAR-ADC design techniques, which are: (1) Low-power SAR-ADC design with split voltage reference, (2) Charge recycling techniques for low-power SAR-ADC design, (3) Low-power SAR-ADC design using two-capacitor arrays, (4) Power reduction techniques by dynamically minimizing SAR-ADC conversion cycles. Matlab simulations are performed to investigate the power saving by the proposed techniques. Simulation results show that significant power reduction can be achieved by using the developed techniques. In addition, design issues such as area overhead, design complexity associated with the proposed low-power techniques are also discussed in the thesis.
| Author | : Simon Louwsma |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 148 |
| Release | : 2010-09-08 |
| Genre | : Technology & Engineering |
| ISBN | : 9048197163 |
Time-interleaved Analog-to-Digital Converters describes the research performed on low-power time-interleaved ADCs. A detailed theoretical analysis is made of the time-interleaved Track & Hold, since it must be capable of handling signals in the GHz range with little distortion, and minimal power consumption. Timing calibration is not attractive, therefore design techniques are presented which do not require timing calibration. The design of power efficient sub-ADCs is addressed with a theoretical analysis of a successive approximation converter and a pipeline converter. It turns out that the first can consume about 10 times less power than the latter, and this conclusion is supported by literature. Time-interleaved Analog-to-Digital Converters describes the design of a high performance time-interleaved ADC, with much attention for practical design aspects, aiming at both industry and research. Measurements show best-inclass performance with a sample-rate of 1.8 GS/s, 7.9 ENOBs and a power efficiency of 1 pJ/conversion-step.
| Author | : Ram Harshvardhan Radhakrishnan |
| Publisher | : |
| Total Pages | : 82 |
| Release | : 2015 |
| Genre | : Analog-to-digital converters |
| ISBN | : |
This thesis work presents a novel technique to reduce the number of conversion cycles for Successive Approximation register (SAR) Analog to Digital Converters (ADC), thereby potentially improving the conversion speed as well as reducing its power consumption. Conventional SAR ADCs employ the binary search algorithm and they update only one bound, either the upper or lower bound, of the search space during one conversion cycle. The proposed method, referred to as the Accelerated-SAR or A-SAR, is capable of updating both the lower and upper bounds in a single conversion cycle. Even in cases that it can update only one bound, it does more aggressively. The proposed technique is implemented in a 10-bit SAR ADC circuit with 0.5V power supply and rail-to-rail input range. To cope with the ultra-low voltage design challenge, Time-to-Digital conversion techniques are used in the implementation. Important design issues are also discussed for the charge scaling array and Voltage Controlled Delay Lines (VCDL), which are important building blocks in the ADC implementation.
| Author | : Sai-Weng Sin |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 147 |
| Release | : 2010-09-29 |
| Genre | : Technology & Engineering |
| ISBN | : 9048197104 |
Analog-to-Digital Converters (ADCs) play an important role in most modern signal processing and wireless communication systems where extensive signal manipulation is necessary to be performed by complicated digital signal processing (DSP) circuitry. This trend also creates the possibility of fabricating all functional blocks of a system in a single chip (System On Chip - SoC), with great reductions in cost, chip area and power consumption. However, this tendency places an increasing challenge, in terms of speed, resolution, power consumption, and noise performance, in the design of the front-end ADC which is usually the bottleneck of the whole system, especially under the unavoidable low supply-voltage imposed by technology scaling, as well as the requirement of battery operated portable devices. Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters will present new techniques tailored for low-voltage and high-speed Switched-Capacitor (SC) ADC with various design-specific considerations.
| Author | : Pedro M. Figueiredo |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 395 |
| Release | : 2009-03-10 |
| Genre | : Technology & Engineering |
| ISBN | : 1402097166 |
Offset Reduction Techniques in High-Speed Analog-to-Digital Converters analyzes, describes the design, and presents test results of Analog-to-Digital Converters (ADCs) employing the three main high-speed architectures: flash, two-step flash and folding and interpolation. The advantages and limitations of each one are reviewed, and the techniques employed to improve their performance are discussed.
| Author | : Walt Kester |
| Publisher | : Newnes |
| Total Pages | : 977 |
| Release | : 2005 |
| Genre | : Computers |
| ISBN | : 0750678410 |
This complete update of a classic handbook originally created by Analog Devices and never previously published offers the most complete and up-to-date reference available on data conversion, from the world authority on the subject. It describes in depth the theory behind and the practical design of data conversion circuits. It describes the different architectures used in A/D and D/A converters - including many advances that have been made in this technology in recent years - and provides guidelines on which types are best suited for particular applications. It covers error characterization and testing specifications, essential design information that is difficult to find elsewhere. The book also contains a wealth of practical application circuits for interfacing and supporting A/D and D/A converters within an electronic system. In short, everything an electronics engineer needs to know about data converters can be found in this volume, making it an indispensable reference with broad appeal. The accompanying CD-ROM provides software tools for testing and analyzing data converters as well as a searchable pdf version of the text. * brings together a huge amount of information impossible to locate elsewhere. * many recent advances in converter technology simply aren't covered in any other book. * a must-have design reference for any electronics design engineer or technician
| Author | : Michael J. Demler |
| Publisher | : Elsevier |
| Total Pages | : 233 |
| Release | : 2012-12-02 |
| Genre | : Technology & Engineering |
| ISBN | : 0080508138 |
This book covers the theory and applications of high-speed analog-to-digital conversion. An analog-to-digital converter takes real-world inputs (such as visual images, temperature readings, and rates of speed) and transforms them into digital form for processing by computer. This book discusses the design and uses of such circuits, with particular emphasis on improving the speed of the conversion process and the accuracy of its output--how well the output is a corresponding digital representation of the output*b1input signal. As computers become increasingly interfaced to the outside world, "ADC" techniques will become ever more important.
| Author | : Behzad Razavi |
| Publisher | : Wiley-IEEE Press |
| Total Pages | : 280 |
| Release | : 1995 |
| Genre | : Computers |
| ISBN | : |
This advanced text and reference covers the design and implementation of integrated circuits for analog-to-digital and digital-to-analog conversion. It begins with basic concepts and systematically leads the reader to advanced topics, describing design issues and techniques at both circuit and system level. Gain a system-level perspective of data conversion units and their trade-offs with this state-of-the art book. Topics covered include: sampling circuits and architectures, D/A and A/D architectures; comparator and op amp design; calibration techniques; testing and characterization; and more!
| Author | : Wei Li |
| Publisher | : |
| Total Pages | : 73 |
| Release | : 2014 |
| Genre | : Successive approximation analog-to-digital converters |
| ISBN | : |
IC designers are continuously facing the challenges from reduced CMOS feature sizes and supply voltages. ADCs that deliver satisfactory resolutions/speeds while utilizing the state-of-the-art technologies to save power are in high demand. The analog circuits are more and more assisted by various digital calibration techniques to get boosted performances. This dissertation is focused on a low-power 12-bit 12.5-MS/s successive approximation (SAR) ADC with a couple of calibration schemes. The performances of the proposed SAR ADC are enhanced in two directions. To reduce the power dissipation, a power saving strategy has been proposed. Also, several foreground calibration methods for SAR ADCs have been proposed to reduce power dissipation and enhance conversion accuracy. The design was fabricated in 40nm CMOS technology. Measurement results after calibration showed a SFDR of 82.2 dB, and a THD improvement of 22.5 dB. Finally, two new schemes to realize teraohm on-chip resistance are presented. One of the schemes utilizes a switched-capacitor array, and the other utilizes a switch-capacitor ladder. Using these schemes, large resistances can be fabricated with standard CMOS process in an affordable chip area.
