FPGA-Based Reconfigurable Physical Layer Architecture for Wireless Applications

FPGA-Based Reconfigurable Physical Layer Architecture for Wireless Applications
Author: James John Chacko
Publisher:
Total Pages: 294
Release: 2017
Genre: Computer-aided engineering
ISBN:

There have been increasing developments in the area of wireless communications based on orthogonal frequency division multiplexing (OFDM). These standards are widely used for their resilience to frequency selective fading and inter symbol interference. OFDM derives this ability through dividing the overall frequency spectrum into smaller narrowband carriers which undergoes manageable and correctable fading through the wireless channel. With the increasing demand to maximize the use of the wireless spectrum both efficiently and securely, there has been significant research in the areas of cognitive, adaptive and secure wireless communication techniques across all the layers of the protocol stack. This dissertation mainly focuses the research developments targeting the physical or baseband layer. Research in these areas that are purely based on software implementations solutions benefit from faster development and turn around times but lack the ability to be tested and validated in real time scenarios as is possible with hardware based solutions. Thus an ideal implementation would be one that incorporates the flexibility offered by software and the real time speed offered by hardware. The flow of data within hardware-implemented baseband kernels is inherently predictable for all communication standards, which helps designers build fast, synchronized and optimized baseband kernels on FPGAs. However off-the-shelf FPGA based SDR architectures often strongly adhere to the few specific standards they are built for and thus are hard to change (in terms of coding rates, modulation, and subcarrier sizes) without substantial effort due to synchronization and data-rate issues. In this dissertation, we develop a programmable and flexible hardware implementation of the physical layer across wireless communication systems that use OFDM techniques. We have developed an OFDM pipeline comprising of all generic physical layer stages in which each stage can be configured at design time or at run time to accommodate different standards as well as different configuration settings within a standard. This flexibility is achieved by designing the overall pipeline to be insensitive to the latencies incurred by individual stages using the concept of state-aware stalling functionality and also with the use of infused control data for shepherding payload across the pipeline. Such a pipeline can be easily used as a research platform to experiment with different OFDM standards as well as for rapid prototyping purposes. The overall system and its performance is characterized in terms of functional correctness, area cost of implementation and flexibility. Experimental and simulation results are obtained and analyzed for the IEEE 802.16 WiMAX and 802.11a/n standards under different coding rates (1/2 and 3/4), modulation schemes (4QAM and 16QAM), and symbol sizes (128 and 64 sub-carriers), all within a common framework that does not require re-synthesis or recompilation because of the inherent capability to perform packet by packet reconfiguration. We also show results on how the flexibility built into the architecture makes it possible to implement non-contiguous OFDM (NC-OFDM) which enables the utilization of sub-carriers efficiently around noisy frequency bands by nulling and avoiding those bands while data is loaded. Keeping the ever growing relevance of cognitive radio research in view, we also built our system to also be flexible in settings user defined inter-packet and inter-frame spacing which comes into prominence in research dealing with adaptive modulation and re-configurable antennas. To further solidify the advantages of the system we built over other platforms we describe two physical layer security techniques that we built that no other hardware based testbeds currently available can implement without significant implementation effort. The first application utilizes the flexibility built into the testbed's packet organization and packet detection modules to be able to modify the wireless packet preamble enabling wireless transmissions between intended parties to go undetected to intruders. The second application utilizes the flexibility built into the interleaver module enabling it to interleave and de-interleave data based on secret keys known only to the intended communicating parties preventing intruders from decoding packets.

Dynamic Reconfiguration Methods in FPGA-based Softawre Defined Radio System for Wireless Mobile Standards

Dynamic Reconfiguration Methods in FPGA-based Softawre Defined Radio System for Wireless Mobile Standards
Author: Ke He
Publisher:
Total Pages: 0
Release: 2012
Genre:
ISBN:

As wireless communication develops and evolves, the number of communication standards continues to increase. Therefore, the design of a Software Defined Radio (SDR) platform, which is aimed at supporting multiple standards and services for consumer applications with a high degree of flexibility, is of growing interest. SDR has been primarily associated with military applications to date. Field Programmable Gate Arrays (FPGAs) are programmable hardware devices which can perform complex calculations with high performance, and therefore, are well suited to wireless communication applications. FPGAs are selected as the reconfigurable devices used to perform various functionalities in the SDR system. However, although FPGAs are reconfigurable and thus can support standards and services switching in the SDR system, conventional SDR systems based on FPGAs can suffer from long reconfiguration overhead, high resource utilisation requirements, high power consumption, and inflexible standards switching. With the conversion from analogue to digital television, a large amount of licensed spectrum is being released, and this is often referred to as "TV white space". The propagation characteristics of these bands are capable of providing longer range and better indoor penetration for consumer compared to other operating frequencies in the Gigahertz range, thus are well suited to wireless communication. Therefore, it will be attractive to integrate TV white space functionality into SDR systems. In this thesis, an efficient design method for Digital Up Converter (DUC) architectures is proposed based on the existing DUC design methods in the Digital Front End (DFE) area. Furthermore, the proposed method can also be applied to TV white space DUC designs to enable the proposed SDR system to support more standards and modes. The novel physical layer architecture for SDR combines two dynamic reconfiguration technologies in supporting multiple standards, including 3rd Generation Partnership Project (3GPP) LTE, IEEE 802.16, IEEE 802.11, WCDMA and extensions to make compatible with white space. In addition, a study of power consumption relating to Partial Reconfiguration (PR) is undertaken based on implementation with the latest PR design flow. The proposed architecture is demonstrated to reduce FPGA reconfiguration overhead, resource utilisation and power consumption significantly, and to increase the degree of design flexibility, expansibility and reusability.

Reconfigurable Logic

Reconfigurable Logic
Author: Pierre-Emmanuel Gaillardon
Publisher: CRC Press
Total Pages: 526
Release: 2018-09-03
Genre: Technology & Engineering
ISBN: 1482262193

During the last three decades, reconfigurable logic has been growing steadily and can now be found in many different fields. Field programmable gate arrays (FPGAs) are one of the most famous architecture families of reconfigurable devices. FPGAs can be seen as arrays of logic units that can be reconfigured to realize any digital systems. Their high versatility has enabled designers to drastically reduce time to market, and made FPGAs suitable for prototyping or small production series in many branches of industrial products. In addition, and thanks to innovations at the architecture level, FPGAs are now conquering segments of mass markets such as mobile communications. Reconfigurable Logic: Architecture, Tools, and Applications offers a snapshot of the state of the art of reconfigurable logic systems. Covering a broad range of architectures, tools, and applications, this book: Explores classical FPGA architectures and their supporting tools Evaluates recent proposals related to FPGA architectures, including the use of network-on-chips (NoCs) Examines reconfigurable processors that merge concepts borrowed from the reconfigurable domain into processor design Exploits FPGAs for high-performance systems, efficient error correction codes, and high-bandwidth network routers with built-in security Expounds on emerging technologies to enhance FPGA architectures, improve routing structures, and create non-volatile configuration flip-flops Reconfigurable Logic: Architecture, Tools, and Applications reviews current trends in reconfigurable platforms, providing valuable insight into the future potential of reconfigurable systems.

Functional Verification of Dynamically Reconfigurable FPGA-based Systems

Functional Verification of Dynamically Reconfigurable FPGA-based Systems
Author: Lingkan Gong
Publisher: Springer
Total Pages: 232
Release: 2014-10-08
Genre: Technology & Engineering
ISBN: 3319068385

This book analyzes the challenges in verifying Dynamically Reconfigurable Systems (DRS) with respect to the user design and the physical implementation of such systems. The authors describe the use of a simulation-only layer to emulate the behavior of target FPGAs and accurately model the characteristic features of reconfiguration. Readers are enabled with this simulation-only layer to maintain verification productivity by abstracting away the physical details of the FPGA fabric. Two implementations of the simulation-only layer are included: Extended Re Channel is a System C library that can be used to check DRS designs at a high level; ReSim is a library to support RTL simulation of a DRS reconfiguring both its logic and state. Through a number of case studies, the authors demonstrate how their approach integrates seamlessly with existing, mainstream DRS design flows and with well-established verification methodologies such as top-down modeling and coverage-driven verification.

Partial Reconfiguration on FPGAs

Partial Reconfiguration on FPGAs
Author: Dirk Koch
Publisher: Springer Science & Business Media
Total Pages: 306
Release: 2012-07-25
Genre: Technology & Engineering
ISBN: 1461412250

This is the first book to focus on designing run-time reconfigurable systems on FPGAs, in order to gain resource and power efficiency, as well as to improve speed. Case studies in partial reconfiguration guide readers through the FPGA jungle, straight toward a working system. The discussion of partial reconfiguration is comprehensive and practical, with models introduced together with methods to implement efficiently the corresponding systems. Coverage includes concepts for partial module integration and corresponding communication architectures, floorplanning of the on-FPGA resources, physical implementation aspects starting from constraining primitive placement and routing all the way down to the bitstream required to configure the FPGA, and verification of reconfigurable systems.

Reconfigurable Computing: Architectures, Tools and Applications

Reconfigurable Computing: Architectures, Tools and Applications
Author: Andreas Koch
Publisher: Springer
Total Pages: 411
Release: 2011-03-15
Genre: Computers
ISBN: 3642194753

This book constitutes the refereed proceedings of the 7th International Symposium on Reconfigurable Computing: Architectures, Tools and Applications, ARC 2011, held in Belfast, UK, in March 2011. The 40 revised papers presented, consisting of 24 full papers, 14 poster papers, and the abstracts of 2 plenary talks, were carefully reviewed and selected from 88 submissions. The topics covered are reconfigurable accelerators, design tools, reconfigurable processors, applications, device architecture, methodology and simulation, and system architecture.

FPGA-based Digital Convolution for Wireless Applications

FPGA-based Digital Convolution for Wireless Applications
Author: Lei Guan
Publisher: Springer
Total Pages: 166
Release: 2017-01-16
Genre: Technology & Engineering
ISBN: 3319520008

This book presents essential perspectives on digital convolutions in wireless communications systems and illustrates their corresponding efficient real-time field-programmable gate array (FPGA) implementations. FPGAs or generic all programmable devices will soon become widespread, serving as the “brains” of all types of real-time smart signal processing systems, like smart networks, smart homes and smart cities. The book examines digital convolution by bringing together the following main elements: the fundamental theory behind the mathematical formulae together with corresponding physical phenomena; virtualized algorithm simulation together with benchmark real-time FPGA implementations; and detailed, state-of-the-art case studies on wireless applications, including popular linear convolution in digital front ends (DFEs); nonlinear convolution in digital pre-distortion (DPD) enabled high-efficiency wireless RF transceivers; and fast linear convolution in massive multiple-input multiple-output (MIMO) systems. After reading this book, students and professionals will be able to: · Understand digital convolution with inside-out information: discover what convolution is, why it is important and how it works. · Enhance their FPGA design skills, i.e., enhance their FPGA-related prototyping capability with model-based hands-on examples. · Rapidly expand their digital signal processing (DSP) blocks: to examine how to rapidly and efficiently create (DSP) functional blocks on a programmable FPGA chip as a reusable intellectual property (IP) core. · Upgrade their expertise as both “thinkers” and “doers”: minimize/close the gap between mathematical equations and FPGA implementations for existing and emerging wireless applications.

Reconfigurable Architectures and Design Automation Tools for Application-Level Network Security

Reconfigurable Architectures and Design Automation Tools for Application-Level Network Security
Author: Sascha Mühlbach
Publisher: Logos Verlag Berlin GmbH
Total Pages: 221
Release: 2015-04-30
Genre: Computers
ISBN: 3832539557

The relevance of the Internet has dramatically grown in the past decades. However, the enormous financial impact attracts many types of criminals. Setting up proper security mechanisms (e.g., Intrusion Detection Systems (IDS)) has therefore never been more important than today. To further compete with today's data transfer rates (10 to 100 Gbit/s), dedicated hardware accelerators have been proposed to offload compute intensive tasks from general purpose processors. As one key technology, reconfigurable hardware architectures, e.g., the Field Programmable Gate Array (FPGA), are of particular interest to this end. This work addresses the use of such FPGAs in the context of interactive communication applications, which goes beyond the regular packet level operations often seen in this area. To support rapid prototyping, a novel FPGA platform (NetStage) has been designed and developed, which provides a communication core for Internet communication and a flexible connection bus for attaching custom applications modules. A hardware honeypot (the MalCoBox) has been set up as a proof-of-concept application. Furthermore, to address the ongoing issue of hardware programming complexity, the domain-specific Malacoda language for abstractly formulating honeypot packet communication dialogs is presented and discussed. An associated compiler translates Malacoda into high-performance hardware modules for NetStage. Together, NetStage and Malacoda address some of the productivity deficiencies often recognized as major hindrances for the more widespread use of reconfigurable computing in communications applications. Finally, the NetStage platform has been evaluated in a real production environment.

Reconfigurable Computing: Architectures, Tools and Applications

Reconfigurable Computing: Architectures, Tools and Applications
Author: Phaophak Sirisuk
Publisher: Springer
Total Pages: 458
Release: 2010-03-10
Genre: Computers
ISBN: 3642121330

Recon?gurable computing (RC) systems have generated considerable interest in the embedded and high-performance computing communities over the past two decades, with ?eld programmable gate arrays (FPGAs) as the leading techn- ogy at the helm of innovation in this discipline. Achieving orders of magnitude performance and power improvements using FPGAs over traditional microp- cessorsis not uncommon for well-suitedapplications. But even with two decades of research and technological advances, FPGA design still presents a subst- tial challenge and often necessitates hardware design expertise to exploit its true potential. Although the challenges to address the design productivity - sues are steep, the promise and the potential of the RC technology in terms of performance, power, size, and versatility continue to attract application design engineers and RC researchers alike. The International Symposium on Applied Recon?gurable Computing (ARC) aims to bring together researchers and practitioners of RC systems with an emphasis on practical applications and design methodologies of this promising technology. This year’s ARC symposium (The sixth ARC symposium) was held in Bangkok, Thailand during March 17–19, 2010, and attracted papers in three primary focus areas:RC applications, RC architectures, and RC design meth- ologies.

Reconfigurable Computing: Architectures, Tools and Applications

Reconfigurable Computing: Architectures, Tools and Applications
Author: Philip Brisk
Publisher: Springer
Total Pages: 253
Release: 2013-03-12
Genre: Computers
ISBN: 3642368123

This book constitutes the thoroughly refereed conference proceedings of the 9th International Symposium on Reconfigurable Computing: Architectures, Tools and Applications, ARC 2013, held in Los Angeles, CA, USA, in March 2013. The 28 revised papers presented, consisting of 20 full papers and 11 poster papers were carefully selected from 41 submissions. The topics covered are applications, arithmetic, design optimization for FPGAs, architectures, place and routing.