Efficient Use Of Time Information In Analog To Digital Converters
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| Author | : Yue Hu |
| Publisher | : |
| Total Pages | : 100 |
| Release | : 2014 |
| Genre | : Analog-to-digital converters |
| ISBN | : |
Time-domain data conversion has recently drawn increased research attention for its highly digital nature in favor of process technology scaling. Also, as the time information being carried by binary voltage, time-domain operation is much less sensitive to voltage noise compared to conventional voltage domain operation. However, for analog-to-digital converter (ADC) application, the challenge lies in the methodology of benefiting from time-domain operation while maintaining/improving the overall data conversion accuracy and power efficiency. This dissertation has a focus on the investigation of novel data conversion topologies based on classic voltage domain operation that is capable of generating time information, to improve ADC resolution, system stability and speed without power penalty. In the first approach, a novel continuous-time (CT) delta-sigma modulator (DSM) using a time-interleaved quantizer is proposed and implemented. Along with the doubled sample rate, the proposed architecture utilizes time information to perform correlated coupling between the two quantizer channels. A 120MS/s CT [delta sigma] ADC using proposed technique is implemented in 0.18 [micro]m CMOS process. The measurement results achieve second order noise coupling from the interleaved quantizer itself without extra phases. More importantly, excess loop delay of two full sample clocks is compensated by time-domain signal coupling; the resulted CT DSM is fully stabilized in 120MHz sampling rate and achieves 11 effective number of bits (ENOB). In the second approach, a new category of pulse-width-modulation (PWM) scheme is proposed and described: time symmetric PWM (TSPWM). An ADC structure is further proposed and implemented utilizing this novel voltage-to-time converter, followed by a first order noise-shaped switched-ring-oscillator (SRO) TDC quantizer. This ADC topology takes advantage of the TDC speed scaling for its digitized operation to boost the overall ADC resolution and signal bandwidth, while the voltage-to-time front-end is able to remain at a much lower speed than the TDC, thanks to the proposed technique. This is the first work that decouples the PWM modulation rate from TDC quantizing speed without distortion penalty. Built in 0.18 [micro]m, the implemented ADC is able to sample at a range from 20MHz to 40MHz, the generated pulse train is quantized by the following SRO TDC at a rate of 400MHz. The prototype chip shows a SFDR improvement over 24dB on the ADC output when TSPWM is used.
| Author | : Simon Louwsma |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 148 |
| Release | : 2010-09-08 |
| Genre | : Technology & Engineering |
| ISBN | : 9048197163 |
Time-interleaved Analog-to-Digital Converters describes the research performed on low-power time-interleaved ADCs. A detailed theoretical analysis is made of the time-interleaved Track & Hold, since it must be capable of handling signals in the GHz range with little distortion, and minimal power consumption. Timing calibration is not attractive, therefore design techniques are presented which do not require timing calibration. The design of power efficient sub-ADCs is addressed with a theoretical analysis of a successive approximation converter and a pipeline converter. It turns out that the first can consume about 10 times less power than the latter, and this conclusion is supported by literature. Time-interleaved Analog-to-Digital Converters describes the design of a high performance time-interleaved ADC, with much attention for practical design aspects, aiming at both industry and research. Measurements show best-inclass performance with a sample-rate of 1.8 GS/s, 7.9 ENOBs and a power efficiency of 1 pJ/conversion-step.
| Author | : Jon Guerber |
| Publisher | : |
| Total Pages | : 167 |
| Release | : 2013 |
| Genre | : Analog-to-digital converters |
| ISBN | : |
In an industrial and consumer electronic marketplace that is increasingly demanding greater real-world interactivity in portable and distributed devices, analog to digital converter efficiency and performance is being carefully examined. The successive approximation (SAR) analog to digital converter (ADC) architecture has become popular for its high efficiency at mid-speed and resolution requirements. This is due to the one core single bit quantizer, lack of residue amplification, and large digital domain processing allowing for easy process scaling. This work examines the traditional binary capacitive SAR ADC time and statistical information and proposes new structures that optimize ADC performance. The Ternary SAR (TSAR) uses the quantizer delay information to enhance accuracy, speed and power consumption of the overall SAR while providing multi-level redundancy. The early reset merged capacitor switching SAR (EMCS) identifies lost information in the SAR subtraction and optimizes a full binary quanitzer structure for a Ternary MCS DAC. Residue Shaping is demonstrated in SAR and pipeline configurations to allow for an extra bit of signal to noise quantization ratio (SQNR) due to multi-level redundancy. The feedback initialized ternary SAR (FITSAR) is proposed which splits a TSAR into separate binary and ternary sub-ADC structures for speed and power benefits with an inter-stage encoding that not only maintains residue shaping across the binary SAR, but allows for nearly optimally minimal energy consumption for capacitive ternary DACs. Finally, the ternary SAR ideas are applied to R2R DACs to reduce power consumption. These ideas are tested both in simulation and with prototype results.
| Author | : Xinpeng Xing |
| Publisher | : Springer |
| Total Pages | : 200 |
| Release | : 2017-10-04 |
| Genre | : Technology & Engineering |
| ISBN | : 3319665650 |
This book discusses both architecture- and circuit-level design aspects of voltage-controlled-oscillator (VCO)-based analog-to-digital converters (ADCs), especially focusing on mitigation of VCO nonlinearity and the improvement of power efficiency. It shows readers how to develop power-efficient complementary-metal-oxide-semiconductor (CMOS) ADCs for applications such as LTE, 802.11n, and VDSL2+. The material covered can also be applied to other specifications and technologies. Design of Power-Efficient Highly Digital Analog-to-Digital Converters for Next-Generation Wireless Communication Systems begins with a general introduction to the applications of an ADC in communications systems and the basic concepts of VCO-based ADCs. The text addresses a wide range of converter architectures including open- and closed-loop technologies. Special attention is paid to the replacement of power-hungry analog blocks with VCO-based circuits and to the mitigation of VCO nonline arity. Various MATLAB®/Simulink® models are provided for important circuit nonidealities, allowing designers and researchers to determine the required specifications for the different building blocks that form the systematic integrated-circuit design procedure. Five different VCO-based ADC design examples are presented, introducing innovations at both architecture and circuit levels. Of these designs, the best power efficiency of a high-bandwidth oversampling ADC is achieved in a 40 nm CMOS demonstration. This book is essential reading material for engineers and researchers working on low-power-analog and mixed-signal design and may be used by instructors teaching advanced courses on the subject. It provides a clear overview and comparison of VCO-based ADC architectures and gives the reader insight into the most important circuit imperfections.
| Author | : Ying Cao |
| Publisher | : Springer |
| Total Pages | : 128 |
| Release | : 2015-02-09 |
| Genre | : Technology & Engineering |
| ISBN | : 3319118420 |
This book focuses on the design of a Mega-Gray (a standard unit of total ionizing radiation) radiation-tolerant ps-resolution time-to-digital converter (TDC) for a light detection and ranging (LIDAR) system used in a gamma-radiation environment. Several radiation-hardened-by-design (RHBD) techniques are demonstrated throughout the design of the TDC and other circuit techniques to improve the TDC's resolution in a harsh environment are also investigated. Readers can learn from scratch how to design a radiation-tolerant IC. Information regarding radiation effects, radiation-hardened design techniques and measurements are organized in such a way that readers can easily gain a thorough understanding of the topic. Readers will also learn the design theory behind the newly proposed delta-sigma TDC. Readers can quickly acquire knowledge about the design of radiation-hardened bandgap voltage references and low-jitter relaxation oscillators, which are introduced in the content from a designer's perspective. · Discusses important aspects of radiation-tolerant analog IC design, including realistic applications and radiation effects on ICs; · Demonstrates radiation-hardened-by-design techniques through a design-test-radiation assessment practice; · Describes a new type of Time-to-Digital (TDC) converter designed for radiation-tolerant application; · Explains the design and measurement of all functional blocks (e.g., bandgap reference, relaxation oscillator) in the TDC.
| Author | : Georges Gielen |
| Publisher | : Springer Nature |
| Total Pages | : 118 |
| Release | : 2022-03-01 |
| Genre | : Technology & Engineering |
| ISBN | : 3030880672 |
This book demonstrates why highly-digital CMOS time-encoding analog-to-digital converters incorporating voltage-controlled oscillators (VCOs) and time-to-digital converters (TDCs) are a good alternative to traditional switched-capacitor S-D modulators for power-efficient sensor, biomedical and communications applications. The authors describe the theoretical foundations and design methodology of such time-based ADCs from the basics to the latest developments. While most analog designers might notice some resemblance to PLL design, the book clearly highlights the differences to standard PLL circuit design and illustrates the design methodology with practical circuit design examples. Describes in detail the design methodology for CMOS time-encoding analog-to-digital converters that can be integrated along with digital logic in a nanometer System on Chip; Assists analog designers with the necessary change in design paradigm, highlighting differences between designing time-based ADCs and traditional analog circuits like switched-capacitor converters and PLLs; Uses a highly-visual, tutorial approach to the topic, including many practical examples of techniques introduced.
| Author | : Taehwan Oh |
| Publisher | : |
| Total Pages | : 87 |
| Release | : 2013 |
| Genre | : Analog-to-digital converters |
| ISBN | : |
As advanced wired and wireless communication systems attempt to achieve higher performance, the demand for high resolution and wide signal bandwidth in their associated ADCs is strongly increased. Recently, time-domain quantization has drawn attention from its scalability in deep submicron CMOS processes. Furthermore, there are several interesting aspects of time-domain quantizer by processing the signal in time rather than only in voltage domain especially for power efficiency. This research focuses on developing a new architecture for power efficient, high resolution ADCs using both voltage and time domain information. As a first approach, a new [delta sigma] ADC based on a noise-shaped two-step integrating quantizer which quantizes the signal in voltage and time domains is presented. Attaining an extra order of noise-shaping from the integrating quantizer, the proposed [delta sigma] ADC manifests a second-order noise-shaping with a first-order loop filter. Furthermore, this quantizer provides an 8b uantization in itself, drastically reducing the oversampling requirement. The proposed ADC also incorporates a new feedback DAC topology that alleviates the feedback DAC complexity of a two-step 8b quantizer. The measured results of the prototype ADC implemented in a 0.13[micro]m CMOS demonstrate peak SNDR of 70.7dB (11.5b ENOB) at 8.1mW power, with an 8x OSR at 80MHz sampling frequency. To further improve ADC performance, a Nyquist ADC based on a time-based pipelined TDC is also proposed as a second approach. In this work, a simple V-T conversion scheme with a cheap low gain amplifier in its first stage and a hybrid time-domain quantization stage based on simple charge pump and capacitive DAC in its backend stages, are also proposed to improve ADC linearity and power efficiency. Using voltage and time domain information, the proposed ADC architecture is beneficial for both resolution and power efficiency, with MSBs resolved in voltage domain and LSBs in time domain. The measured results of the prototype ADC implemented in a 0.13[micro]m CMOS demonstrate peak SNDR of 69.3dB (11.2b ENOB) at 6.38mW power and 70MHz sampling frequency. The FOM is 38.2fJ/conversion-step.
| Author | : Stephan Henzler |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 132 |
| Release | : 2010-03-10 |
| Genre | : Technology & Engineering |
| ISBN | : 9048186285 |
Micro-electronics and so integrated circuit design are heavily driven by technology scaling. The main engine of scaling is an increased system performance at reduced manufacturing cost (per system). In most systems digital circuits dominate with respect to die area and functional complexity. Digital building blocks take full - vantage of reduced device geometries in terms of area, power per functionality, and switching speed. On the other hand, analog circuits rely not on the fast transition speed between a few discrete states but fairly on the actual shape of the trans- tor characteristic. Technology scaling continuously degrades these characteristics with respect to analog performance parameters like output resistance or intrinsic gain. Below the 100 nm technology node the design of analog and mixed-signal circuits becomes perceptibly more dif cult. This is particularly true for low supply voltages near to 1V or below. The result is not only an increased design effort but also a growing power consumption. The area shrinks considerably less than p- dicted by the digital scaling factor. Obviously, both effects are contradictory to the original goal of scaling. However, digital circuits become faster, smaller, and less power hungry. The fast switching transitions reduce the susceptibility to noise, e. g. icker noise in the transistors. There are also a few drawbacks like the generation of power supply noise or the lack of power supply rejection.
| Author | : Heemin Yi Yang |
| Publisher | : |
| Total Pages | : 258 |
| Release | : 2006 |
| Genre | : |
| ISBN | : |
(Cont.) This converter could be useful in low-power hearing aids after analog gain control has been performed on a microphone front-end. An 8 bit audio version of our converter in a 0.18 [mu] m process consumes 960nW and yields an energy-efficiency of 0.12pJ per quantization level, perhaps the lowest ever reported. This converter may be useful in biomedical and sensor-network applications where energy-efficiency is paramount. Our algorithm has inherent advantages in time-to-digital conversion. It can be generalized to easily digitize power-law functions of its input, and it can be used in an interleaved architecture if higher speed is desired.
| Author | : Franco Maloberti |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 454 |
| Release | : 2007-02-22 |
| Genre | : Science |
| ISBN | : 0387324852 |
This book is the first graduate-level textbook presenting a comprehensive treatment of Data Converters. The advancement of digital electronics urged the availability of a still missing support for teaching and self-learning analog-digital interfaces at many levels: the specification, the conversion methods and architectures, the circuit design and the testing. This book, after the necessary study of the background theoretical elements, covers aspects and provide elements for a deep and comprehensive knowledge. The breath and the level of details of topics is enhanced by introductory material in each chapter and the use of many examples, most of them in the form of computer behavioral simulations. The examples and the end-of-chapter problems help in understanding and favor self-practice using tools that are effective for training and for design activity. Data Converters is a textbook that is also essential for engineering professionals as it was written for responding to a shortage of organically organized material on the topic. The book assumes a solid background in analog and digital circuits as well as a working knowledge of simulation tools for circuit and behavioral analysis. A background on statistical analysis is also helpful, though not strictly necessary. Coverage of all the basic elements essential for a clear understanding of sampling, quantization, noise in sampled-data systems and mathematical tools for sampled-data linear systems Comprehensive definition of the parameters used to specify data converters and necessary for understanding product data sheets Coverage of all the architectures used in Nyquist-rate data converters and detailed study of features, limits and design techniques Detailed study of oversampled and Sigma-Delta converters with simulation examples and use of spectra and histograms for a clear understanding of features and limit if the noise shaping Coverage of digital correction and calibration techniques for enhancing performances Use of theory and intuitive views to explain circuits and systems operation and limits Coverage of testing methods and description of the data processing used for testing and characterization Extensive use of Simulink and Matlab in examples and problem sets to assist reader comprehension and favor deeper study
