With emerging millimeter wave applications including automotive radars, wireless transmission of high-definition content, and possibly 5G mobile communications, low cost and high performance power amplifiers are key for enabling a commercial mass market. Silicon technologies offer cost advantages but typically suffer from low breakdown voltage and low Q passive elements yielding low power density and low efficiency. This thesis presents millimeter wave power amplifiers implemented in main stream silicon technologies. The task of obtaining large output power from low breakdown silicon devices is addressed by the use of stacking and power combining techniques. The design of a Q-band amplifier implemented in IBM 0.13um SiGe HBT process featuring on-chip corporate combining is first described. Stacking of bipolar transistors is introduced, together with novel low impedance biasing circuits to enable high breakdown voltage while extending the output swings. The fabricated amplifier delivered 24.7 dBm of maximum output power at 39 GHz, and 6.5% efficiency at 5.2 V without degradation. Alternatively, free-space combining can eliminate lossy on-chip combiners allowing for higher power and efficiency. A chip of 8 unit amplifiers implemented in 45nm CMOS SOI feeding a 2x2 array of differentially-fed patch antennas is demonstrated. With this chip, using CMOS stacking techniques, high output power (28 dBm) was achieved from a 3-stage amplifier operating at 45 GHz. When coupled to the antennas, the array provided an equivalent isotropic radiated power (EIRP) of 40 dBm (10 W), and a larger system comprising 4 chips feeding a 2x8 array was shown to deliver an EIRP of 50 dBm (100 W) at 45 GHz, while demonstrating, for the first time, a total RF power of 33 dBm which is a record in silicon at this frequency. The estimated peak PAE for both arrays are 13.5% and 10.7%, respectively. Finally, power amplifiers implemented in SOI technology can suffer from severe self-heating. The thermal behavior of CMOS SOI PAs is evaluated using 3D thermal simulations, and the effects of the back-end interconnect as well as the layout on the overall thermal resistance are discussed. The models were verified against measurements for an individual FET using the output conductance method. For a stacked-FET PA fabricated in 45nm CMOS SOI, the models reveal an excessive temperature rise of 150C for the FETs at maximum power, hence simple ideas were proposed to improve the thermal resistance of SOI circuits, with limited impact on electrical performance.