A Low Power High Speed High Resolution Zero Crossing Based Pipelined Analog To Digital Converter
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| Author | : Soonkyun Shin |
| Publisher | : |
| Total Pages | : 127 |
| Release | : 2014 |
| Genre | : |
| ISBN | : |
In this dissertation, techniques with zero-crossing based circuits (ZCBC) to achieve high speed and high resolution in scaled technologies with very low intrinsic gain are proposed. A coarse phase followed by a level shifting capacitor for a fine phase current source is employed to achieve higher accuracy and sub-ADC flash comparators are strobed immediately after the coarse phase for high frequency operation. The systematic offset voltage between the coarse and fine phases manifests itself as systematic offset in the sub-ADC comparators. This offset is caused by the coarse phase undershoot and the fine phase overshoot. It is cancelled with background calibration by residue range correction circuits within the following stage's sub-ADC. The sub-ADC's random comparator offset is calibrated with a discrete-time charge-pump based background calibration technique. A prototype device based on the aforementioned concepts was realized in a 55nm CMOS process. The ADC occupies 0.282 mm2 and dissipates 30.7mW. It achieves 64.6dB SNDR and 82.9 dBc SFDR at 200 MS/s for a FOM of 111 fJ/conversion-step. The SNDR degrades gracefully above the designed sampling frequency to 62.9 dB at 250 MS/s, and remains above 50 dB at 300 MS/s. To minimize the power consumption further when using the ZCD technique, a dynamic biasing technique is proposed and employed. The bias current feeding the ZCD preamplifier is dynamic and depends on input ramp voltage. This method reduces current consumption by supplying bias current only when needed during a zero crossing event. This ADC consumes 27.1mW and achieved 61.2 dB SNDR for a FOM of 143 fJ/step.
| Author | : Yue Jack Chu |
| Publisher | : |
| Total Pages | : 94 |
| Release | : 2008 |
| Genre | : |
| ISBN | : |
In this thesis, I describe a zero-crossing based pipelined ADC. Unlike traditional pipelined ADCs, this work does not use any op-amps in the signal path. The use of zero-crossing based circuits made it possible to achieve a much better figure of merit. The ADC is design to operate at 200MS/s with a resolution of 12 bits. The simulated results suggest that the target performance is achievable with less than 10 mW of power. This design's figure of merit is at least an order of magnitude better than any existing designs that have comparable speed and accuracy performance. The design will be fabricated later to be tested in silicon.
| Author | : Sunghyuk Lee |
| Publisher | : |
| Total Pages | : 76 |
| Release | : 2010 |
| Genre | : |
| ISBN | : |
A zero-crossing based pipelined analog-to-digital converter (ADC) has been designed and is fabricated in a 65nm CMOS process. The highly digital implementation characteristic of the zero-crossing detection technique enables energy efficient operation and voltage scaling. Supply voltage scaling based on the required sampling frequency and resolution provides high energy efficiency over a wide range of sampling frequencies and resolutions. A two phase charge transfer scheme (course charge transfer and fine charge transfer) is used to achieve high speed and high resolution. Using switched capacitor circuit, two phase charge transfer scheme is implemented without increasing power and circuit complexity.
| Author | : Amir Zjajo |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 311 |
| Release | : 2010-10-29 |
| Genre | : Technology & Engineering |
| ISBN | : 9048197252 |
With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power, low-voltage A/D converters that can be realized in a mainstream deep-submicron CMOS technology. However, the discrepancies between lithography wavelengths and circuit feature sizes are increasing. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. The inherent randomness of materials used in fabrication at nanoscopic scales means that performance will be increasingly variable, not only from die-to-die but also within each individual die. Parametric variability will be compounded by degradation in nanoscale integrated circuits resulting in instability of parameters over time, eventually leading to the development of faults. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. In an attempt to address these issues, Low-Power High-Resolution Analog-to-Digital Converters specifically focus on: i) improving the power efficiency for the high-speed, and low spurious spectral A/D conversion performance by exploring the potential of low-voltage analog design and calibration techniques, respectively, and ii) development of circuit techniques and algorithms to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover errors continuously. The feasibility of the described methods has been verified by measurements from the silicon prototypes fabricated in standard 180nm, 90nm and 65nm CMOS technology.
| Author | : Weitao Li |
| Publisher | : Springer |
| Total Pages | : 181 |
| Release | : 2017-08-01 |
| Genre | : Technology & Engineering |
| ISBN | : 3319620126 |
This book is a step-by-step tutorial on how to design a low-power, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) integrated CMOS analog-to-digital (AD) converter, to respond to the challenge from the rapid growth of IoT. The discussion includes design techniques on both the system level and the circuit block level. In the architecture level, the power-efficient pipelined AD converter, the hybrid AD converter and the time-interleaved AD converter are described. In the circuit block level, the reference voltage buffer, the opamp, the comparator, and the calibration are presented. Readers designing low-power and high-performance AD converters won’t want to miss this invaluable reference. Provides an in-depth introduction to the newest design techniques for the power-efficient, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) AD converter; Presents three types of power-efficient architectures of the high-resolution and high-speed AD converter; Discusses the relevant circuit blocks (i.e., the reference voltage buffer, the opamp, and the comparator) in two aspects, relaxing the requirements and improving the performance.
| Author | : Kyung Ryun Kim |
| Publisher | : Stanford University |
| Total Pages | : 128 |
| Release | : 2010 |
| Genre | : |
| ISBN | : |
In high-performance pipelined analog-to-digital converters (ADCs), the residue amplifiers dissipate the majority of the overall converter power. Therefore, finding alternatives to the relatively inefficient, conventional class-A circuit realization is an active area of research. One option for improvement is to employ class-AB amplifiers, which can, in principle, provide large drive currents on demand and improve the efficiency of residue amplification. Unfortunately, due to the simultaneous demand for high speed and high gain in pipelined ADCs, the improvements seen in class-AB designs have so far been limited. This dissertation presents the design of an efficient class-AB amplification scheme based on a pseudo-differential, single-stage and cascode-free architecture. Nonlinear errors due to finite DC gain are addressed using a deterministic digital background calibration that measures the circuit imperfections in time intervals between normal conversion cycles of the ADC. As a proof of concept, a 12-bit 30-MS/s pipelined ADC was realized using class-AB amplifiers with the proposed digital calibration. The prototype ADC occupies an active area of 0.36 mm2 in 90-nm CMOS. It dissipates 2.95 mW from a 1.2-V supply and achieves an SNDR of 64.5 dB for inputs near the Nyquist frequency. The corresponding figure of merit is 72 fJ/conversion-step.
| Author | : 曾千鑑 |
| Publisher | : |
| Total Pages | : |
| Release | : 2016 |
| Genre | : |
| ISBN | : |
| Author | : Gabriele Manganaro |
| Publisher | : Cambridge University Press |
| Total Pages | : 251 |
| Release | : 2011-11-17 |
| Genre | : Technology & Engineering |
| ISBN | : 1139504746 |
Need to get up to speed quickly on the latest advances in high performance data converters? Want help choosing the best architecture for your application? With everything you need to know about the key new converter architectures, this guide is for you. It presents basic principles, circuit and system design techniques and associated trade-offs, doing away with lengthy mathematical proofs and providing intuitive descriptions upfront. Everything from time-to-digital converters to comparator-based/zero-crossing ADCs is covered and each topic is introduced with a short summary of the essential basics. Practical examples describing actual chips, along with extensive comparison between architectural or circuit options, ease architecture selection and help you cut design time and engineering risk. Trade-offs, advantages and disadvantages of each option are put into perspective with a discussion of future trends, showing where this field is heading, what is driving it and what the most important unanswered questions are.
| Author | : Keh-La Lin |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 270 |
| Release | : 2006-01-14 |
| Genre | : Technology & Engineering |
| ISBN | : 0306487268 |
One of the main trends of microelectronics is toward design for integrated systems, i.e., system-on-a-chip (SoC) or system-on-silicon (SoS). Due to this development, design techniques for mixed-signal circuits become more important than before. Among other devices, analog-to-digital and digital-to-analog converters are the two bridges between the analog and the digital worlds. Besides, low-power design technique is one of the main issues for embedded systems, especially for hand-held applications. Modular Low-Power, High-Speed CMOS Analog-to-Digital Converter for Embedded Systems aims at design techniques for low-power, high-speed analog-to-digital converter processed by the standard CMOS technology. Additionally this book covers physical integration issues of A/D converter integrated in SoC, i.e., substrate crosstalk and reference voltage network design.
| Author | : Ashutosh Ravindra Joharapurkar |
| Publisher | : |
| Total Pages | : 174 |
| Release | : 2000 |
| Genre | : |
| ISBN | : |
The stupendous growth in wireless communication systems and portable devices has made it increasingly important to obtain power reduction in integrated circuits. In portable devices such as cellular phones, camcorders and digital cameras longer battery life is desired. With the limited stored energy available in a reasonably sized battery, minimizing the power dissipation in integrated circuits is becoming increasingly important. In today's world of Information Superhighways, huge amounts of data are stored, accessed and transmitted over a short duration of time. In many systems the input data is inherently analog in nature but it is generally much more practical to process this data in a digital format. The conversion of the analog input data to a digital format is attained in a front-end analog to digital (A/D) converter. The high-speed data transfer rates thus require high conversion rates of the front-end A/D interface. To achieve these higher speeds more power is generally required in the A/D. The goal of this research is to build a very low power ADC with good speed and resolution performance. Target specifications were a sampling rate of 2OMS/s, 10-bit resolution and low voltage operation (3.3V) in a standard CMOS technology. The latest technology available for this product is a 0.35[Mu] CMOS process. The simulation results showed that the ADC dissipated 6.7mW power at the target specifications and does not require any calibration. This power dissipation is less than half the power dissipation in the ADCs reported so far with comparable resolution and speed in CMOS process.
