With the growing demand for portable communications devices, power consumption has become increasingly critical in VLSI designs. In mixed-signal circuits, the push for lower supply voltage to reduce power dissipation in digital systems has forced analog systems to lower their supply voltage as well. This thesis deals with the design of a low power low voltage analog-to-digital converter (ADC) that operates from a single 1 V power supply. Two circuit techniques are utilized to enhance the performance of the converter. First, floating-point technique is employed to improve the dynamic range of the converter by providing a non-uniform quantization of the analog input. This allows the ADC to achieve a wide dynamic range without using high-resolution components. Second, current-mode technique is chosen because it offers characteristics such as good signal swings, high speed and small circuit area. The ADC was implemented using a 0.5 [mu]m, 1V CMOS process with low threshold voltage transistors. Simulation results of the core ADC cell indicate an 8-bit resolution while dissipating only 170 [mu]W. The complete floating-point ADC exhibits a dynamic range of 12 bits, a conversion time of 63 [mu]s and a power dissipation of 450 [mu]W. The total area excluding bonding pads is 1 mm 2.