11th Asian Test Symposium (ATS'02)

11th Asian Test Symposium (ATS'02)
Author:
Publisher: IEEE Computer Society Press
Total Pages: 464
Release: 2002
Genre: Computers
ISBN:

Held in Guam in November of 2002, the symposium on the test technologies and research issues related to silicon chip production, resulted in the 74 papers presented here. The papers are organized into sections related to the symposium sessions on test generation, on-line testing, analog and mixed si

Test Generation of Crosstalk Delay Faults in VLSI Circuits

Test Generation of Crosstalk Delay Faults in VLSI Circuits
Author: S. Jayanthy
Publisher: Springer
Total Pages: 161
Release: 2018-09-20
Genre: Technology & Engineering
ISBN: 981132493X

This book describes a variety of test generation algorithms for testing crosstalk delay faults in VLSI circuits. It introduces readers to the various crosstalk effects and describes both deterministic and simulation-based methods for testing crosstalk delay faults. The book begins with a focus on currently available crosstalk delay models, test generation algorithms for delay faults and crosstalk delay faults, before moving on to deterministic algorithms and simulation-based algorithms used to test crosstalk delay faults. Given its depth of coverage, the book will be of interest to design engineers and researchers in the field of VLSI Testing.

Multi-run Memory Tests for Pattern Sensitive Faults

Multi-run Memory Tests for Pattern Sensitive Faults
Author: Ireneusz Mrozek
Publisher: Springer
Total Pages: 142
Release: 2018-07-06
Genre: Technology & Engineering
ISBN: 3319912046

This book describes efficient techniques for production testing as well as for periodic maintenance testing (specifically in terms of multi-cell faults) in modern semiconductor memory. The author discusses background selection and address reordering algorithms in multi-run transparent march testing processes. Formal methods for multi-run test generation and many solutions to increase their efficiency are described in detail. All methods presented ideas are verified by both analytical investigations and numerical simulations. Provides the first book related exclusively to the problem of multi-cell fault detection by multi-run tests in memory testing process; Presents practical algorithms for design and implementation of efficient multi-run tests; Demonstrates methods verified by analytical and experimental investigations.

ATS 2003

ATS 2003
Author:
Publisher: Institute of Electrical & Electronics Engineers(IEEE)
Total Pages: 544
Release: 2003
Genre: Computers
ISBN: 9780769519517

The Asian Test Symposium provides an international forum for engineers and researchers from all countries of the World, especially from Asia, to present and discuss various aspects of system, board and device testing with design, manufacturing and field considerations in mind. ATS 2003's papers shares state-of-the-art ideas and technologies in testing.

VLSI Design and Test for Systems Dependability

VLSI Design and Test for Systems Dependability
Author: Shojiro Asai
Publisher: Springer
Total Pages: 792
Release: 2018-07-20
Genre: Technology & Engineering
ISBN: 4431565949

This book discusses the new roles that the VLSI (very-large-scale integration of semiconductor circuits) is taking for the safe, secure, and dependable design and operation of electronic systems. The book consists of three parts. Part I, as a general introduction to this vital topic, describes how electronic systems are designed and tested with particular emphasis on dependability engineering, where the simultaneous assessment of the detrimental outcome of failures and cost of their containment is made. This section also describes the related research project “Dependable VLSI Systems,” in which the editor and authors of the book were involved for 8 years. Part II addresses various threats to the dependability of VLSIs as key systems components, including time-dependent degradations, variations in device characteristics, ionizing radiation, electromagnetic interference, design errors, and tampering, with discussion of technologies to counter those threats. Part III elaborates on the design and test technologies for dependability in such applications as control of robots and vehicles, data processing, and storage in a cloud environment and heterogeneous wireless telecommunications. This book is intended to be used as a reference for engineers who work on the design and testing of VLSI systems with particular attention to dependability. It can be used as a textbook in graduate courses as well. Readers interested in dependable systems from social and industrial–economic perspectives will also benefit from the discussions in this book.

Design and Test Technology for Dependable Systems-on-chip

Design and Test Technology for Dependable Systems-on-chip
Author: Raimund Ubar
Publisher: IGI Global
Total Pages: 580
Release: 2011-01-01
Genre: Computers
ISBN: 1609602145

"This book covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC)"--

Responsive Computer Systems: Steps Toward Fault-Tolerant Real-Time Systems

Responsive Computer Systems: Steps Toward Fault-Tolerant Real-Time Systems
Author: Donald Fussell
Publisher: Springer Science & Business Media
Total Pages: 283
Release: 2012-12-06
Genre: Computers
ISBN: 1461522714

Responsive Computer Systems: Steps Towards Fault-Tolerant Real-Time Systems provides an extensive treatment of the most important issues in the design of modern Responsive Computer Systems. It lays the groundwork for a more comprehensive model that allows critical design issues to be treated in ways that more traditional disciplines of computer research have inhibited. It breaks important ground in the development of a fruitful, modern perspective on computer systems as they are currently developing and as they may be expected to develop over the next decade. Audience: An interesting and important road map to some of the most important emerging issues in computing, suitable as a secondary text for graduate level courses on responsive computer systems and as a reference for industrial practitioners.

Labs on Chip

Labs on Chip
Author: Eugenio Iannone
Publisher: CRC Press
Total Pages: 1351
Release: 2018-09-03
Genre: Medical
ISBN: 1351832069

Labs on Chip: Principles, Design and Technology provides a complete reference for the complex field of labs on chip in biotechnology. Merging three main areas— fluid dynamics, monolithic micro- and nanotechnology, and out-of-equilibrium biochemistry—this text integrates coverage of technology issues with strong theoretical explanations of design techniques. Analyzing each subject from basic principles to relevant applications, this book: Describes the biochemical elements required to work on labs on chip Discusses fabrication, microfluidic, and electronic and optical detection techniques Addresses planar technologies, polymer microfabrication, and process scalability to huge volumes Presents a global view of current lab-on-chip research and development Devotes an entire chapter to labs on chip for genetics Summarizing in one source the different technical competencies required, Labs on Chip: Principles, Design and Technology offers valuable guidance for the lab-on-chip design decision-making process, while exploring essential elements of labs on chip useful both to the professional who wants to approach a new field and to the specialist who wants to gain a broader perspective.